8.8

IC warning case temperature detection (TWARN)

The TWARN pin is an active low open drain output. This pin is active if the IC case temperature exceeds TCSD.

According to the PCB thermal design and RthJC value, this function warns about a PCB overheating condition.

The TWARN bit is also available through SPI. This bit is not latched: the TWARN pin is low only while the case

overtemperature condition is active (TC > TCSD) and is released when this condition is removed (TC < TCR).

8.9

Fault indication (FAULT)

The FAULT pin is an open drain active low fault indication pin. One or more of the following conditions activates

this pin:

•

Channel overtemperature (OVT)

This pin is activated when at least one of the channels is in junction overtemperature.

Unlike the SPI fault detection bits, this signal is not latched: the FAULT pin is low only when the fault condition is

active and is released if the input driving signal is OFF or after the OVT protection condition has been removed.

This last event occurs if the channel temperature decreases below the threshold level and the case temperature

has not exceeded TCSD or is below TCR. This means that the FAULT pin is low only while the junction

overtemperature is active (TJ > TTSD) and is released after this condition has been removed (TJ < TR and TC <

TCR).

•

Parity check fail

When SPI mode is used (SEL2 = H), if a parity check fault of the incoming SPI frame is detected or counted, CLK

rising edges are different by a multiple of 8, the FAULT pin is kept low. When counted CLK rising edges are a

multiple of 8 and the parity check is valid, the FAULT pin is kept high.

8.10

Power Good (PG)

The PG terminal is an open drain, which indicates the status of the supply voltage. When the VCC supply voltage

reaches the Vsth1 threshold, PG goes into a high impedance state. It goes into a low impedance state when the

VCC falls below the Vsth2 threshold.

In 16-bit SPI mode, a PG bit is also available. This bit is set high when the Power Good diagnostic is active;

otherwise, it is cleared.

Figure 11. Power Good diagnostic

Vcc

PG

VPGH2

VPGH1

GIPG030420151221LM

8.11

Programmable watchdog counter reset (WD)

If SEL2 = H, and the WD_EN = H, then the embedded watchdog counter is enabled. An H-L transition on the WD

pin resets the watchdog counter.

If the counter elapses before the H-L transition on the WD pin, then the IC enters into an internal reset state

where all the outputs are disabled. To restart normal operation a negative pulse must be applied to the WD pin.

The WD_EN pin should be connected through an external divider to VREG.

The watchdog time is fixed in the following table:

IPS8200HQ, IPS8200HQ-1

IC warning case temperature detection (TWARN)

DS14313 - Rev 2

page 17/36