Electronic Components Datasheet Search
  English  ▼

X  

IPS8200HQ Datasheet(PDF) 20 Page - STMicroelectronics

Part # IPS8200HQ
Description  Octal high-side smart power solid-state relay with serial/parallel selectable interface on-chip
PDF  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

IPS8200HQ Datasheet(HTML) 20 Page - STMicroelectronics

Back Button IPS8200HQ Datasheet HTML 16Page - STMicroelectronics IPS8200HQ Datasheet HTML 17Page - STMicroelectronics IPS8200HQ Datasheet HTML 18Page - STMicroelectronics IPS8200HQ Datasheet HTML 19Page - STMicroelectronics IPS8200HQ Datasheet HTML 20Page - STMicroelectronics IPS8200HQ Datasheet HTML 21Page - STMicroelectronics IPS8200HQ Datasheet HTML 22Page - STMicroelectronics IPS8200HQ Datasheet HTML 23Page - STMicroelectronics IPS8200HQ Datasheet HTML 24Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 20 / 36 page
background image
At the same time, the IC transfers to the microcontroller a 16-bit fault frame where the first 8 bits indicate a
channel fault (OVT) condition (each bit, set to ‘1’, indicates an OVT event), the following 4 bits provide general
fault condition information. FB_OK: this bit is related to the DC/DC regulation: at the DC/DC turn-on, this bit is low
and becomes high after FB rises above 90% of the nominal VFB voltage and a correct SPI communication
occurrs. If the FB voltage falls below 80% of the nominal VFB voltage, this bit is zero; TWARN (IC warning case
temperature), PC (parity check fail, the bit, set to ‘1’, indicates a PC fail or the length is not a multiple of 8), and
PG (Power Good, see Section 8.10). The last 4 bits are used as parity check bits and communication error
conditions (see command 16-bit frame):
P0 = F0
⊕F1⊕F2⊕F3⊕F4⊕F5⊕F6⊕F7
P1 = PC
⊕FB_OK⊕F1⊕F3⊕F5⊕F7
P2 = PG
⊕TWARN⊕F0⊕F2⊕F4⊕F6
nP0 = not P0
where
⊕istheXORoperatorsymbol.
Table 17. Fault 16-bit frame (from IC to MCU)
MSB
LSB
F7
F6
F5
F4
F3
F2
F1
F0
FB_OK
TWARN
PC
PG
P2
P1
P0
nP0
Channel indications are latched and cleared only after a communication.
9.3
Daisy chaining
The IPS8200HQ/HQ-1 can be daisy chained by connecting the MOSI port of the micro-controller to the SDI pin of
the first IC of the chain; the SDO pin of the first IC of the chain to the SDI pin of the second (and similarly for the
next ICs of the chain); and the SDO pin of the last IC of the chain to the MISO port of the micro-controller. See an
example in Figure 14
Figure 14. Example of daisy chaining connection
IPS8200HQ, IPS8200HQ-1
Daisy chaining
DS14313 - Rev 2
page 20/36



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com