AD3552R datasheet(40/66 Pages) AD

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Data Sheet

AD3542R

THEORY OF OPERATION

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Rev. C | 40 of 66

ERR_STATUS Register

VREF Detection

The REF_RANGE_ERR_STATUS bit in the ERR_STATUS register

is set when the reference voltage drops below 1 V for more than

5 ms. The error is detected irrespective of the reference voltage

source, whether it is generated internally or provided externally via

the VREF pin. This feature is useful to detect an interruption in the

external reference voltage or an overload condition on the VREF pin

when the internal reference is shared with another device.

SPI Mode Error

The SPI mode error is produced during streaming when the ad-

dress pointer crosses the boundary between the secondary and

the primary region with the SPI interface configured in synchronous

dual SPI mode or dual SPI mode because this region can only

be accessed in classic SPI mode. The DUAL_SPI_STREAM_EX-

CEEDS_DAC_ERR_STATUS bit is set in the ERR_STATUS regis-

ter.

The AD3542R includes an internal CRC for the register map and

the read only memory (ROM). The CRC is executed every 4.1 μs,

and only includes the primary region of the register map because

the secondary region is expected to be continuously written. The

CRC can be disabled by clearing the MEM_CRC_EN bit in the

INTERFACE_CONFIG_D register. If a CRC error is detected, the

MEM_CRC_ERR_STATUS bit is set in the ERR_STATUS register.

It is advisable to reset the device if this error occurs.

Reset Status

The RESET_ STATUS bit in the ERR_STATUS register indicates

that the AD3542R has been reset, either internally (POR or SW

reset) or externally (via the RESET pin). The RESET_STATUS bit

is set when the POR completes correctly. It is useful to detect

unexpected reset conditions, such as a dip in power supply, and

take corrective actions.

The RESET_STATUS bit causes the assertion of the ALERT pin

and it is not maskable. Therefore, it must be cleared after reset or

power-up to be able to detect new events via the ALERT signal.

INTERFACE_STATUS_A Register

Device Busy

The INTERFACE_NOT_READY bit in the INTERFACE_STATUS_A

know when the device is ready to receive data from the controller.

SPI Clock Counter

The error reported in the CLOCK_COUNTING_ERR bit is pro-

duced when the number of SCLK cycles is not in accordance

with the amount required to shift a multiple of 8 bits, taking into

account the SPI mode (dual or single) and the DDR mode. The

CLOCK_COUNTING_ERR bit is set in the ERR_STATUS register.

Valid combinations are shown in Table 15.

Table 15. Clock Cycles Required to Transfer One Byte

SPI Mode

DDR

Clock Cycles for 1 Byte

Single SPI

Yes

Dual SPI

Yes

SPI CRC

The INVALID_OR_NO_CRC bit in the INTERFACE_STATUS_A

the SPI transaction is missing or it does not match the calculated

value. To clear this error, write 1 to this bit. Note that because CRC

is enabled, this SPI transaction must have a valid CRC code to

succeed.

Write to Read Only Register

If the host tries to write to a read only register, the

WRITE_TO_READ_ONLY_REGISTER bit field is asserted in the

INTERFACE_STATUS_A register. To clear this error, write 1 to the

WRITE_TO_READ_ONLY_REGISTER bit.

Partial Register Access

The PARTIAL_REGISTER_ ACCESS bit in the INTERFACE_STA-

TUS_A register is set when a multibyte register is accessed for read

or write partially, which means that the transaction ends before all

the bytes of a multibyte register have been accessed. To clear this

error, write 1 to the PARTIAL_REGISTER_ ACCESS bit.

Invalid Access

When the host tries to access an invalid register address, the REG-

ISTER_ADDRESS_INVALID bit is set in the INTERFACE_STA-

TUS_A register. To clear this error, write 1 to this bit.

ALERT PIN

When one of the errors listed in Table 14 is detected and its

corresponding bit in the ERR_ALARM_MASK register is set to 0,

the ALERT pin is asserted. This pin can be used as an interrupt line

for the CPU to take action when an error condition arises.

In addition, the ALERT pin is asserted when the RESET_STATUS

bit is asserted in the ERR_STATUS register. This condition is not

maskable. Therefore, the RESET_STATUS bit must be cleared

after initialization to use the ALERT pin. If the pin remains asserted

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