AD3552R datasheet(28/66 Pages) AD

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Data Sheet

AD3542R

THEORY OF OPERATION

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disabled setting the CHx_CHANNEL_POWERDOWN bit in POW-

ERDOWN_CONFIG register.

VREF

The AD3542R has an internal 2.5 V voltage reference with a

3 ppm/°C temperature coefficient that is enabled at power-up. The

VREF pin is in high impedance at power-up to avoid electrical

problems. If the internal reference must be used externally, the

REFERENCE_VOLTAGE_SEL bits in the REFERENCE_CONFIG

Table 9.

When the external reference is selected, the VREF pin behaves as

an input.

Table 9. Voltage Reference Selection

REFERENCE_VOLTAGE_SEL

Source

VREF I/O

Internal

Floating

Internal

2.5 V

External

Input

External

Input

SPI REGISTER MAP ACCESS

SPI Frame Synchronization

The CS signal frames data during an SPI transaction. A falling edge

on CS enables the digital interface and initiates an SPI transaction.

Each SPI transaction consists of at least one instruction phase and

data phase, as described in the Instruction Phase section and the

Data Phase section. For all SPI transactions, data is aligned MSB

first. Deasserting CS during an SPI transaction terminates part or

all of the data transfer and disables the digital interface. If CS is

deasserted (returned high) after one or more register addresses

are issued, those registers are written or read, but any partially

addressed register is ignored. Figure 80 and Figure 81 outline the

stages of a basic SPI write and read frame, respectively, for the

AD3542R in register mode.

Detailed timing diagrams for register read and write operations are

shown in Figure 2 through Figure 8. The timing specification is

given in the Timing Characteristics section.

The AD3542R SPI protocol is flexible and can be configured to suit

the needs of a variety of digital hosts. Data from multiple registers

can be accessed in a single SPI frame, enabling efficient device

configuration. All the different access modes are described in the

Single Instruction Mode section and the Streaming Mode section.

Instruction Phase

Every SPI frame starts with an instruction phase. The instruction

phase immediately follows the falling edge of CS that initiates the

SPI transaction.

The instruction phase consists of a read/write bit (R/W) followed

by a register address word. Setting R/W low initiates a write

instruction, whereas setting R/W high initiates a read instruction.

The register address word specifies the address of the register to

be accessed. The register address word is 7 bits in length (7‑bit

addressing) by default. If required, 15‑bit addressing can be ena-

bled by setting the SHORT_INSTRUCTION bit to 0 in the INTER-

FACE_CONFIG_B register. If the user is using single instruction

mode, each register read or write transaction in a single SPI frame

also begins with an instruction phase. If the user is using streaming

mode, only one instruction phase is required per SPI frame to

access a set of consecutive registers. See the Single Instruction

Mode section and the Streaming Mode section for instructions on

selecting and using these modes.

Data Phase

The data phase immediately follows the instruction phase, as

shown in Figure 80 and Figure 81. The data phase can include

the data for a single-byte register, a multibyte register, or multiple

registers depending on the selected registers and access modes.

See the Single Instruction Mode section, Streaming Mode section,

and Address Direction section for descriptions of how these modes

affect the read and write data in the data phase.

In a write operation, the content of the addressed register is updat-

ed immediately after the SCLK edge, which shifts in the last bit

of the register data, regardless if it is a one-byte, two-byte, or

three-byte register. Multibyte registers cannot be written partially, as

explained in the Multibyte Registers section.

In a read operation, the content of the addressed register starts

shifting out on the first SCLK edge of the data phase.

Data must be written to the AD3542R configuration registers in full

bytes to ensure they are updated. If the data phase of an SPI write

transaction does not include the entire byte of data for the register

being updated, the contents of the register are not updated, and the

CLOCK_COUNTING_ERROR bit in the INTERFACE_STATUS_A

Figure 80. Basic SPI Write Frame

Figure 81. Basic SPI Read Frame

Multibyte Registers

Some AD3542R registers consist of 2 or 3 bytes of data stored

in adjacent addresses and are referred to as multibyte registers.

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