AD3552R datasheet(63/66 Pages) AD

63 / 66 page

Data Sheet

AD3542R

REGISTERS

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Rev. C | 63 of 66

Table 52. Bit Descriptions for CH_SELECT_24B (Continued)

Bits

Bit Name

Settings

Description

Reset

Access

SEL_CH0

Select Channel 0. When this bit is set, data written to the INPUT_PAGE_24B register is

copied to the CH0_INPUT_24B register and data written to the DAC_PAGE_24B register is

copied to the CH0_DAC_24B register.

0x0

R/W

0 No operation.

1 Copy to corresponding register in Channel 0.

Input Page Register, Precision Mode

Address: 0x42, Reset: 0x000000, Name: INPUT_PAGE_24B

This register is used to write data to one or both DAC input registers according to the configuration of the SEL_CHx bits in the CH_SE-

LECT_24B register.

Table 53. Bit Descriptions for INPUT_PAGE_24B

Bits

Bit Name

Settings

Description

Reset

Access

[23:8]

INPUT_PAGE

Input Page Data. Following a write to this register, the DAC code loaded into this register

is copied into the input register of any channels selected in the CH_SELECT_24B

0x0

R/W

[7:0]

RESERVED

Reserved.

0x0

Software LDAC Register, Precision Mode

Address: 0x45, Reset: 0x00, Name: SW_LDAC_24B

This register is used to trigger a data transfer between the input registers and the DAC registers. It is the software equivalent of pulsing the

LDAC line low.

Table 54. Bit Descriptions for SW_LDAC_24B

Bits

Bit Name

Settings

Description

Reset

Access

[7:2]

RESERVED

Reserved.

0x0

SW_LDAC_CH1

Software LDAC for Channel 1. Setting this bit transfers contents from the

CH1_INPUT_24B register to the CH1_DAC_24B register. This bit automatically resets

after being written.

0x0

0 No operation.

1 Load DAC 1.

SW_LDAC_CH0

Software LDAC for Channel 0. Setting this bit transfers contents from the

CH0_INPUT_24B register to the CH0_DAC_24B register. This bit automatically resets

after being written.

0x0

0 No operation.

1 Load DAC 0.

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