AD3552R datasheet(60/66 Pages) AD

60 / 66 page

Data Sheet

AD3542R

REGISTERS

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Rev. C | 60 of 66

Software LDAC Register, Fast Mode

Address: 0x32, Reset: 0x00, Name: SW_LDAC_16B

This register is used to trigger a data transfer between the input registers and the DAC registers. It is the software equivalent of pulsing the

LDAC line low.

Table 45. Bit Descriptions for SW_LDAC_16B

Bits

Bit Name

Settings

Description

Reset

Access

[7:2]

RESERVED

Reserved.

0x0

SW_LDAC_CH1

Software LDAC for Channel 1. Setting this bit transfers contents from the

CH1_INPUT_16B register to the CH1_DAC_16B register. This bit automatically resets

after being written.

0x0

0 No operation.

1 Load DAC 1.

SW_LDAC_CH0

Software LDAC for Channel 0. Setting this bit transfers contents from the

CH0_INPUT_16B register to the CH0_DAC_16B register. This bit automatically resets

after being written.

0x0

0 No operation.

1 Load DAC 0.

Input Register for Channel 0, Fast Mode

Address: 0x33, Reset: 0x0000, Name: CH0_INPUT_16B

This register contains the data to be transferred to the DAC register using one of the various trigger options, hardware LDAC, software LDAC,

or automatic transfer.

Table 46. Bit Descriptions for CH0_INPUT_16B

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

INPUT_DATA0

Channel 0 Input Data.

0x0

R/W

Input Register for Channel 1, Fast Mode

Address: 0x35, Reset: 0x0000, Name: CH1_INPUT_16B

This register contains the data to be transferred to the DAC register using one of the various trigger options, hardware LDAC, software LDAC,

or automatic transfer.

AD3552R Datasheet(PDF) 60 Page - Analog Devices

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