AD3552R datasheet(65/66 Pages) AD

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Data Sheet

AD3542R

APPLICATIONS INFORMATION

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Rev. C | 65 of 66

POWER SUPPLY RECOMMENDATIONS

The AD3542R does not have any restriction for power supply

sequencing. The chip incorporates a power monitor for AVDD and

DVDD that releases the internal reset when both rails are within

specification. Nevertheless, the recommended sequence to turn on

the supply rails is GND, AVDD, DVDD, VLOGIC because it minimizes

the power-up glitch. PVDD and PVSS are independent of the three

previous supplies and can be switched on at any time. A small

glitch (<100 mV) appears when PVDD reaches 2 V.

It is recommended to connect AGND and DGND together and have

a single solid ground plane.

AVDD has a constant power consumption that is independent of the

update rate. The main caution for this rail is ensuring that noise

level is low in the high frequencies, where AC PSRR is lower.

DVDD has a variable power consumption that depends on the

update rate and the SPI bus mode. Dynamic current has fast

variations that cause the rail to be noisy. If DVDD is derived from

AVDD, a filter is recommended in addition to the LDO to completely

remove the effect on the DAC output.

VLOGIC has very low current demand that depends on the SPI bus

mode and clock rate. Power consumption is maximum in readout

operations in dual SPI mode.

The recommended decoupling for the supply rails and the analog

lines is shown in Figure 99.

RFB1_0

RFB2_0

RFB4_0

RFB1_1

RFB2_1

RFB4_1

VOUT0

VOUT1

CFB0

CFB1

Figure 99. Recommended Application Circuit

The decoupling capacitors on CVREF can be adjusted to achieve

the desired trade-off between noise corner frequency and power-up

glitch amplitude.

The CFB0 and CFB1 capacitors are used to adjust the bandwidth

of the internal TIA to achieve the optimal step response with the

minimum overshoot.

Use capacitors with NP0 dielectric for the feedback capacitors

and any other capacitors on the path of the output voltage to

avoid the derating caused by low frequency voltage variations.

The decoupling capacitors for the supply rails and CVREF can use

materials with high dielectric constant because the voltage on these

lines is constant.

LAYOUT GUIDELINES

The pin configuration of the AD3542R, shown in Figure 10, is

arranged in a way that facilitates the layout of the EVAL-AD3542R.

Most digital high speed lines are located on one side of the chip,

with the analog functions of the DAC symmetrically distributed

along the other three sides. This arrangement allows routing the

digital lines straight away from the analog functions, leaving space

for analog parts to be placed around the other three sides, as

shown in Figure 100.

Figure 100. EVAL-AD3542R Component Arrangement and Layout

The following list is a few recommendations to observe to obtain the

best performance:

►

Keep the CFBx capacitors close to the AD3542R with short

traces to minimize noise pickup because it is connected to a high

impedance node internally.

►

Keep switching regulators and fast dV/dt signals away from the

feedback loops of the DAC. Any μA induced on these lines

becomes a mV at the output of the DAC.

►

Do not overlap analog and digital signals. If a crossing cannot be

avoided, it must be done at 45° or 90°.

►

Route digital lines using traces with a constant characteristic

impedance to avoid signal integrity problems that result in timing

violations in DDR mode and crosstalk between signals. The

traces must have a continuous ground plane in an adjacent

layer. When changing layers, ensure that the destination layer is

referred to another ground plane and the traces have the same

characteristic impedance. Place a via connecting both ground

planes near the via of the digital line. If the destination layer

is referred to a power plane, it must be continuous along the

path of the line and a decoupling capacitor between power and

ground must be placed close to the via of the digital line.

AD3552R Datasheet(PDF) 65 Page - Analog Devices

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