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MP2328 Datasheet(PDF) 3 Page - Monolithic Power Systems |
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MP2328 Datasheet(HTML) 3 Page - Monolithic Power Systems |
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3 / 24 page ![]() MP2328 – 28V, 2A, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS MP2328 Rev. 1.0 www.MonolithicPower.com 3 12/11/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name Description 1 PG Power good output. This pin is an open-drain output. PG pulls low when the IC is disabled. PG can be pulled up to another DC source. Note that if PG is pulled up to an external voltage, PG does not de-assert (logic low) if the input power is off. It is recommended to pull PG up to VOUT so that PG can de-assert when the input power is off. 2 VIN Supply voltage. The MP2328 operates from a 4.5V to 28V input rail. Place a ceramic capacitor on VIN to decouple the input rail. Connect VIN using a wide PCB trace. 3 SW Switch output. Connect SW using a wide PCB trace. 4 GND System ground. Reference ground of the regulated output voltage. GND requires additional considerations when designing the PCB layout. Connect GND with copper traces and vias. 5 BST Bootstrap. Connect a capacitor between the SW and BST pins to form a floating supply across the high-side switch driver. Generally, use a 0.1µF bootstrap capacitor. 6 EN Enable pin. EN is a digital input that turns the buck converter on or off. When the power supply of the control circuit is ready, drive EN high to turn the buck converter on. Drive EN low to turn the converter off. Connect EN to VIN through a resistive voltage divider for automatic start-up. The EN voltage should not exceed 6V. 7 SS Soft start. Connect an external capacitor to SS to configure the soft-start time for the switch-mode converter. 8 FB Feedback. Connect FB to the tap of an external resistor divider from the output to GND to set the output voltage. ABSOLUTE MAXIMUM RATINGS (1) VIN ................................................. -0.3V to +30V VSW ....................................................................... -0.3V (-5V for <10ns) to +30V (+32V for <10ns) VBST.....................................................VSW + 5.5V All other pins ................................... -0.3V to +6V PG pin current.......................................... 5mA (2) Continuous power dissipation (TA = 25°C) (3) ……………………………………………. 2.27W (4) Junction temperature ................................ 150°C Lead temperature...................................... 260°C Storage temperature.................-65°C to +150°C ESD Ratings Human body model (HBM) .....................±2000V Charged device model (CDM) .................±750V Recommended Operating Conditions (5) Supply voltage (VIN) ......................... 4.5V to 28V Output voltage (VOUT)........................................... ……………………0.5V to 0.95 x VIN or 16V Max Operating junction temp (TJ).....-40°C to +125°C Thermal Resistance θJA θJC SOT583 EVL2328-TL-00A (4)..................55......21.... °C/W JESD51-7 (6)……………………130….60… °C/W Notes: 1) Exceeding these ratings may damage the device. 2) When PG pin is pulled up to power source, the current should be limited to lower than the maximum value. 3) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ (MAX), the junction-to- ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX) - TA) / θJA. Exceeding the maximum allowable power dissipation can cause excessive die temperature, and the converter may go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 4) Measured on EVL2328-TL-00A, 2-layer, 63.5mmx63.5mm PCB. 5) The device is not guaranteed to function outside of its operating conditions. 6) The value of θJA given in this table is only valid for comparison with other packages and cannot be used for design purposes. These values were calculated in accordance with JESD51-7, and simulated on a specified JEDEC board. They do not represent the performance obtained in an actual application. |
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