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35FS6500 Datasheet(PDF) 36 Page - NXP Semiconductors

Part # 35FS6500
Description  Grade 0 safety power system basis chip with CAN FD transceiver
PDF  139 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

35FS6500 Datasheet(HTML) 36 Page - NXP Semiconductors

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NXP Semiconductors
35FS4500-35FS6500-ASILB
Grade 0 safety power system basis chip with CAN FD transceiver
12.5.1 Fail-safe machine state diagram
aaa-037812
- RSTb/FSxb asserted low
- RSTb asserted low
- 8 s timer running
- RSTb/FSxb asserted low
- RSTB released, FSxb asserted low
- 8 s timer running
- Unlock SPI init registers
- 256 ms open window
- RSTB released, FSxB asserted low
- 8 s timer running
- Start WD windowing
- 8 s timer running
- RSTb delay running
- RSTb asserted low
- 8 s timer running
- FSxb asserted low
- FSxb released
- RSTb/FSxb asserted low
- 8 s timer starts (running)
- RSTb/FSxb asserted low
- 8 s timer reset (not running)
- RSTb/FSxb asserted low
- 8 s timer running
-VCORE/VCCA/VAUX OFF-
-VPRE/VCAN OFF-
-RSTb = LOW-
-FSxb = LOW-
- FSxb asserted low
Wait FS
start-up
Power Down
From
Anywhere
ABIST1
Release
RTSb
Release
FSxb
Wait
VPRE
Wait
VREG
SELECT pin
configuration
LPOFF-
SLEEP
Deep Fail-
save
From anywhere
after FS start-up
From INIT_FS
or NORMAL_WD
ABIST2
(VAUX or FS1b)
Assert RSTb
Assert FSxb
INIT_FS
NORMAL_WD
13 ms elapsed
VPRE > VPRE_UV
VPRE < VPRE_UV
IO_0=0
VPRE < VPRE_UV
1 ms elapsed
VCORE > VCORE_UV
& VCCA > VCCA_UV
ABIST1 Done
External
RST
No DFS &
RST delay = 8 s
DFS &
(RST delay = 8 s or
FLT_err_count = 6)
No activate RSTB &
RSTb delay expired
Activate
RSTb
External
RST
WD Not OK
External
RST
No external RST &
No activate RSTb
WD OK
No activate FSxb
FLT_err_count = 0
& ABISTx ok & FS_OUT ok
& No activate RSTB
FLT_err_count=0
& ABISTx ok
& FS_OUT ok
SPI command
SPI command
ABIST Done
Activate
RSTb
Activate
RSTb
Activate
FSxB
PORB = 1 and
VPRE > VPRE_UV
PORB = 0
Figure 14. Detailed fail-safe state diagram
35FS4500-35FS6500-ASILB
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 3 — 5 August 2024
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