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35FS6500 Datasheet(PDF) 76 Page - NXP Semiconductors |
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35FS6500 Datasheet(HTML) 76 Page - NXP Semiconductors |
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76 / 139 page  NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver Description SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both main and fail-safe logics. Other errors flagged by SPI_ CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) SPI_FS_CLK Reset condition Power on reset Description Invalid SPI access (wrong write or read, write to INIT registers in normal mode, wrong address), concerns fail-safe Logic only 0 No error 1 SPI violation SPI_FS_REQ Reset condition Power on reset Description SPI parity bit error detection, concerns fail-safe logic only 0 Parity bit OK 1 Parity bit error SPI_FS_PARITY Reset condition Power on reset Table 17. MISO bits description...continued 13.2.4 Main logic register address table Table 18 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for main logic. Address Register FS/M A4 A3 A2 A1 A0 Hex Write description Table ref. INIT_VREG 0 0 0 0 0 1 #1(01h) Write during INIT phase then read only Table 21 INIT_WU1 0 0 0 0 1 0 #2(02h) Write during INIT phase then read only Table 23 INIT_WU2 0 0 0 0 1 1 #3(03h) Write during INIT phase then read only Table 25 INIT_INT 0 0 0 1 0 0 #4(04h) Write during INIT phase then read only Table 27 INIT_INH_INT 0 0 0 1 0 1 #5(05h) Write during INIT phase then read only Table 29 LONG_DURATION_TIMER 0 0 0 1 1 0 #6(06h) Write during normal and read Table 31 NOT USED 0 0 0 1 1 1 #7(07h) N/A N/A HW_CONFIG 0 0 1 0 0 0 #8(08h) Read only Table 33 WU_SOURCE 0 0 1 0 0 1 #9(09h) Read only Table 35 DEVICE_ID 0 0 1 0 1 0 #10(0Ah) Read only Table 37 IO_INPUT 0 0 1 0 1 1 #11(0Bh) Read only Table 39 DIAG_VPRE 0 0 1 1 0 0 #12(0Ch) Read only Table 41 DIAG_VCORE 0 0 1 1 0 1 #13(0Dh) Read only Table 43 DIAG_VCCA 0 0 1 1 1 0 #14(0Eh) Read only Table 45 DIAG_VAUX 0 0 1 1 1 1 #15(0Fh) Read only Table 47 DIAG_VSUP_VCAN 0 1 0 0 0 0 #16(10h) Read only Table 49 DIAG_CAN_1 0 1 0 0 0 1 #17(11h) Read only Table 51 DIAG_CAN_2 0 1 0 0 1 0 #18(12h) Read only Table 53 DIAG_SPI 0 1 0 0 1 1 #19(13h) Read only Table 55 NOT USED 0 1 0 1 0 0 #20(14h) N/A N/A MODE 0 1 0 1 0 1 #21(15h) Write during normal and read Table 57 REG_MODE 0 1 0 1 1 0 #22(16h) Write during normal and read Table 59 Table 18. Register mapping of main logic 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback 76 / 139 |
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