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35FS6500 Datasheet(PDF) 96 Page - NXP Semiconductors |
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35FS6500 Datasheet(HTML) 96 Page - NXP Semiconductors |
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96 / 139 page  NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver Description Request for an INT pulse 0 No Request 1 Request for an INT pulse INT_REQ Reset condition Power on reset Description Report if INIT mode of the main logic state machine is entered 0 Not in INIT mode 1 INIT mode INIT Reset condition Power on reset Description Report if normal mode of the main logic state machine is entered 0 Not in normal mode 1 Normal mode NORMAL Reset condition Power on reset Description Report if the device resumes from deep fail-safe mode 0 Not in deep fail-safe 1 Resume from deep fail-safe DFS Reset condition Power on reset/read Description Report if the device resumes from LPOFF-sleep or LPOFF_AUTO_WU mode 0 Not in LPOFF 1 Resume from LPOFF LPOFF Reset condition Power on reset/read Description Secured bits based on write bits Secure 3:0 Secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 Table 58. Mode description and configuration of the bits (default value in bold)...continued 13.3.20 REG_MODE Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 0 1 0 1 1 0 P VCORE_ EN VCCA_EN VAUX_EN VCAN_EN Secure_3 Secure_2 Secure_1 Secure_0 MISO SPI_G WU_G CAN_G Reserved IO_G VPRE _G VCORE _G VOTHERS_ G Reserved Reserved Reserved Reserved VCORE_ EN VCCA_EN VAUX_EN VCAN_EN Table 59. REG_MODE register description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU_G CAN_G Reserved IO_G VPRE _G VCORE _G VOTHERS_ G Reserved Reserved Reserved Reserved VCORE_ EN VCCA_EN VAUX_EN VCAN_EN 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback 96 / 139 |
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