35FS6500 datasheet(46/139 Pages) NXP

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NXP Semiconductors

35FS4500-35FS6500-ASILB

Grade 0 safety power system basis chip with CAN FD transceiver

The switch S1 is opened by default and must be closed by a SPI command, due to the FS1B_DLY_REQ bit in

the SF_OUTPUT_REQUEST register, before releasing the FS1B pin.

12.5.6.2 tDURATION operation

In tDURATION configuration, FS1B is asserted low at the same time as FS0B for a configurable duration, and is

automatically released after tDURATION timing (Figure 26). The FS1B activation duration is configurable via the

SPI from 0 ms to 3150 ms with the combination of the FS1B_TIME_3:0 and FS1B_TIME_RANGE bits. This

digital duration is generated by the fail-safe logic with an accuracy of ±10 %.

FS0B

Device and ECU is safe state

FS1B

tDURATION

FS1B automatic release

after tDURATION

FS0B release

by the SPI

FS1B asserted after tDURATION

aaa-037760

Failure detected

Figure 26. tDURATION operation

12.5.7 Fail-safe outputs (FS0B and FS1B) release

When the fail-safe outputs FS0B and consequently FS1B are asserted low by the device due to a fault, some

conditions must be validated before allowing these pins to be released by the device. These conditions are:

• ABIST2_FS1B_OK=1 if part number with FS1B

• ABIST2_VAUX_OK=1 except if VAUX_FS_OV_1:0=VAUX_FS_UV_1:0="00"

• Fault is removed

• Fault error counter must be at ’0’

• Close the S1 switch (FS1B_DLY_DRV bit = 1)

• RELEASE_FSxB register must be filled with the right value

12.5.7.1 RELEASE_FSxB register

When a fault is removed and the fault error counter changes back to level ’0’, a right word must be filled in

the RELEASE_FSxB register. The value depends on the current LFSR. LSB, MSB must be swapped, and a

negative operation per bit must be applied.

FS0B and FS1B can be released independently or at the same time, depending on the configuration of the first

three bits of the RELEASE_FSxB register (Table 12).The RELEASE_FSxB write command should be done after

an LFSR read command. If FS0B and FS1B are released sequentially, the procedure must be done a first time

for FS0B, and a second time for FS1B.

Note: The LFSR register is used to secure the release of FSxB pins. It can be configured during the INIT phase

but can also be written at any moment in Normal mode. It is impossible to write 0xFFFF and 0x0000 in LFSR

is ignored.

LFSR_7:0

Release FS0B

RELEASE_FSxB_7:0

Release FS1B

RELEASE_FSxB_7:0

Table 12. RELEASE_FSxB register based on LFSR value

35FS4500-35FS6500-ASILB

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Product data sheet

Rev. 3 — 5 August 2024

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