35FS6500 datasheet(66/139 Pages) NXP

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NXP Semiconductors

35FS4500-35FS6500-ASILB

Grade 0 safety power system basis chip with CAN FD transceiver

Figure 51 describes the independent state machine of long duration timer (LDT). After a POR of the device, the

LDT is in idle mode waiting for configuration. The after-run timer function starts when the LDT_ENABLE bit is

set by SPI. The wake-up timer function starts when the device enters in LPOFF mode.

• When function 1 is selected and the counter reaches the after run value (EOT), an interrupt is generated and

the counter is stopped. The counter must be disabled (~ENABLE) before reading its value and enabled again.

• When function 2 is selected and the counter reaches the after run value (EOT), the device goes to LPOFF

mode and the counter is stopped. The counter must be disabled (~ENABLE) before reading its value and

enabled again.

• When function 3 is selected and the counter reaches the after run value (EOT), the device goes to LPOFF

mode. The counter is reset and restart to count. When the counter reaches the wake-up value (EOT), the

device wakes up and the counter is stopped. The counter must be disabled (~ENABLE) before reading its

value and enabled again.

• When function 4 is selected and the counter reaches the wake-up value (EOT), the device wakes up and the

counter is stopped. The counter must be disabled (~ENABLE) before reading its value and enabled again.

• When function 5 is selected and the counter overflows (OVRFLW), the device wakes up and the counter is

stopped. The counter must be disabled (~ENABLE) before reading its value and enabled again. Overflow

means counter max value is reached (all 24 bits at logic 1).

• When function 5 is selected and the devices wakes up by CAN, or IO, the counter is running. The counter

must be disabled (~ENABLE) before reading its value and enabled again.

aaa-039994

AFTER RUN

count

IDLE

STOP

WAKE UP

count

F3 & EOT

* F3 & EOT -> LPOFF

~ ENABLE

ENABLE &

(F1|F2|F3)

(F1|F2) & EOT

* F1 & EOT -> INTB

* F2 & EOT -> LPOFF

EOT: End Of Timer

OVRFLW: Timer Overflow

FX: Function X selected

WU: Wake up

~ ENABLE

POR

ENABLE &

LPOFF & (F4|F5)

* F5 & WU

by CAN, IO

((F3|F4) & EOT) | (F5 & OVRFLW)

* (F3|F4) & EOT -> WU

* F5 & OVRFLW -> WU

Figure 51. Long duration timer state machine

12.9 CAN transceiver

The CAN (controller area network) transceiver provides the physical interface between the CAN protocol

controller of an MCU and the physical dual wires CAN-bus. The 35FS4500/35FS6500 integrated CAN interface

is compliant with flexible data standard at 2.0 Mbit/s. It offers excellent EMC and ESD performance, and meets

the ISO 11898-2(11) and ISO 11898-5(12) standards.

35FS4500-35FS6500-ASILB

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 August 2024

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