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AM3359 Datasheet(PDF) 161 Page - Texas Instruments

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Part # AM3359
Description  AM335x Sitara™ Processors
PDF  256 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM3359 Datasheet(HTML) 161 Page - Texas Instruments

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com
SPRS717L – OCTOBER 2011 – REVISED MARCH 2020
Submit Documentation Feedback
Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
Peripheral Information and Timings
Copyright © 2011–2020, Texas Instruments Incorporated
7.7.2.2.2.2 Compatible JEDEC DDR2 Devices
Table 7-46 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 or x8 DDR2-533 speed grade DDR2 devices.
Table 7-46. Compatible JEDEC DDR2 Devices (Per Interface)(1)
NO.
PARAMETER
MIN
MAX
UNIT
1
JEDEC DDR2 device speed grade(2)
DDR2-533
2
JEDEC DDR2 device bit width
x8
x16
bits
3
JEDEC DDR2 device count
1
2
devices
4
JEDEC DDR2 device terminal count(3)
60
84
terminals
(1) If the DDR2 interface is operated with a clock frequency less than 266 MHz, lower-speed grade DDR2 devices may be used if the
minimum clock period specified for the DDR2 device is less than or equal to the minimum clock period selected for the AM335x DDR2
interface.
(2) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backward compatibility.
(3) 92-terminal devices are also supported for legacy reasons. New designs will migrate to 84-terminal DDR2 devices. Electrically, the 92-
and 84-terminal DDR2 devices are the same.
7.7.2.2.2.3 PCB Stackup
The minimum stackup required for routing the AM335x device is a 4-layer stackup as shown in Table 7-
47. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal
integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
Table 7-47. Minimum PCB Stackup(1)
LAYER
TYPE
DESCRIPTION
1
Signal
Top signal routing
2
Plane
Ground
3
Plane
Split power plane
4
Signal
Bottom signal routing
(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these
signals on layer 1, therefore requiring routing of some signals on layer 4. When this is done, the signal routes on layer 4 must not cross
splits in the power plane.



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