TDA8376 datasheet(22/44 Pages) PHILIPS

22 / 44 page

1996 Jan 26

Philips Semiconductors

Objective speciﬁcation

I2C-bus controlled PAL/NTSC TV processors

TDA8376; TDA8376A

FLYBACK PULSE INPUT (PIN 41)

VHSW

switching voltage level for horizontal

blanking

−

0.4

−

Vϕ2(SW)

switching level for phase-2 loop

−

4.0

−

V41(max)

maximum input voltage

note 7

−

8.0

−

input impedance

note 7

−

Ω

SANDCASTLE PULSE OUTPUT (PIN 39)

V39

output voltage

during burst key

4.8

5.3

5.8

during blanking

1.8

2.0

2.2

pulse width

burst key pulse

3.3

3.5

3.7

µs

vertical blanking (50 Hz)

−

lines

vertical blanking (60 Hz)

−

lines

Vclamp

clamping voltage level for vertical

guard detection

−

2.7

−

I39(min)

minimum input current to activate

guard detection

−−

0.5

I39(max)

maximum allowable input current

2.5

−−

delay of start of burst key to start of

sync

−

5.4

−µs

Vertical synchronization and geometry correction

VERTICAL OSCILLATOR; note 15

ffr

free running frequency

−

50/60

−

flock

locking frequency range

−

64.5

divider value not locked

−

625/525

−

lines

locking range

488

−

722

lines/

frame

VERTICAL RAMP GENERATOR (PIN 50)

V50(p-p)

sawtooth voltage amplitude

(peak-to-peak value)

VS = 1FH;

C = 100 nF; R = 39 k

Ω

−

3.5

−

Idis

discharge current

−

Icharge

charge current set by external

resistor

note 16

−

−µA

vertical slope control range

63 steps

−20

−

+20

∆I

charge current increase

f = 60 Hz

−

V50L

LOW level voltage of ramp

−

2.07

−

VERTICAL DRIVE OUTPUTS (PINS 47 AND 48)

Idiff(p-p)

differential output current

(peak-to-peak value)

VA = 1FH

−

0.95

−

ICM

common mode output current

−

400

−µA

output voltage

−

4.0

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

TDA8376 Datasheet(PDF) 22 Page - NXP Semiconductors

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