M68HC08 datasheet(206/288 Pages) FREESCALE

206 / 288 page

DDC12AB Interface

Data Sheet

MC68HC908BD48 — Rev. 2.1

206

DDC12AB Interface

Freescale Semiconductor

When the DDRR is read by the CPU, the receive buffer full flag is cleared

(RXBF = 0), and the next received data is loaded to the DDRR. Each

time when new data is loaded to the DDRR, the RXIF interrupt flag is set,

indicating that new data is available in DDRR.

The sequence of events for slave receive and master receive are

illustrated in Figure 15-8.

15.7 Programming Considerations

When the DDC module detects an arbitration loss in master mode, it will

release both SDA and SCL lines immediately. But if there are no further

STOP conditions detected, the module will hang up. Therefore, it is

recommended to have time-out software to recover from such ill

condition. The software can start the time-out counter by looking at the

BB (Bus Busy) flag in the DMCR and reset the counter on the completion

of one byte transmission. If a time-out occur, software can clear the DEN

bit (disable DDC module) to release the bus, and hence clearing the BB

flag. This is the only way to clear the BB flag by software if the module

hangs up due to a no STOP condition received. The DDC can resume

operation again by setting the DEN bit.

M68HC08 Datasheet(PDF) 206 Page - Freescale Semiconductor, Inc