M68HC08 datasheet(202/288 Pages) FREESCALE

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DDC12AB Interface

Data Sheet

MC68HC908BD48 — Rev. 2.1

202

DDC12AB Interface

Freescale Semiconductor

15.6.5 DDC Status Register (DSR)

RXIF — DDC Receive Interrupt Flag

This flag is set after the data receive register (DDRR) is loaded with a

new received data. Once the DDRR is loaded with received data, no

more received data can be loaded to the DDRR register until the CPU

reads the data from the DDRR to clear RXBF flag. RXIF generates an

interrupt request to CPU if the DIEN bit in DCR is also set. This bit is

cleared by writing "0" to it or by reset; or when the DEN = 0.

1 = New data in data receive register (DDRR)

0 = No data received

TXIF — DDC Transmit Interrupt Flag

This flag is set when data in the data transmit register (DDTR) is

downloaded to the output circuit, and that new data can be written to

the DDTR. TXIF generates an interrupt request to CPU if the DIEN bit

in DCR is also set. This bit is cleared by writing "0" to it or when the

DEN = 0.

1 = Data transfer completed

0 = Data transfer in progress

MATCH — DDC Address Match

This flag is set when the received data in the data receive register

(DDRR) is an calling address which matches with the address or its

extended addresses (EXTAD=1) specified in the DADR register.

1 = Received address matches DADR

0 = Received address does not match

Address:

$0019

Bit 7

654321

Bit 0

Read:

RXIF

TXIF

MATCH

SRW

RXAK

SCLIF

TXBE

RXBF

Write:

Reset:

00001010

= Unimplemented

Figure 15-5. DDC Status Register (DSR)

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