M68HC08 datasheet(203/288 Pages) FREESCALE

203 / 288 page

DDC12AB Interface

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

DDC12AB Interface

203

SRW — DDC Slave Read/Write

This bit indicates the data direction when the module is in slave mode.

It is updated after the calling address is received from a master

device. SRW = 1 when the calling master is reading data from the

module (slave transmit mode). SRW = 0 when the master is writing

data to the module (receive mode).

1 = Slave mode transmit

0 = Slave mode receive

RXAK — DDC Receive Acknowledge

When this bit is cleared, it indicates an acknowledge signal has been

received after the completion of 8 data bits transmission on the bus.

When RXAK is set, it indicates no acknowledge signal has been

detected at the 9th clock; the module will release the SDA line for the

master to generate "stop" or "repeated start" condition. Reset sets this

bit.

1 = No acknowledge signal received at 9th clock bit

0 = Acknowledge signal received at 9th clock bit

SCLIF — SCL Interrupt Flag

This flag is set when a falling edge is detected on the SCL line, only if

DDC1EN bit is set. SCLIF generates an interrupt request to CPU if the

SCLIEN bit in DCR is also set. SCLIF is cleared by writing "0" to it or

when the DCC1EN = 0, or DEN = 0. Reset clears this bit.

1 = Falling edge detected on SCL line

0 = No falling edge detected on SCL line

TXBE — DDC Transmit Buffer Empty

This flag indicates the status of the data transmit register (DDTR).

When the CPU writes the data to the DDTR, the TXBE flag will be

cleared. TXBE is set when DDTR is emptied by a transfer of its data

to the output circuit. Reset sets this bit.

1 = Data transmit register empty

0 = Data transmit register full

M68HC08 Datasheet(PDF) 203 Page - Freescale Semiconductor, Inc