M68HC08 datasheet(207/288 Pages) FREESCALE

207 / 288 page

DDC12AB Interface

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

DDC12AB Interface

207

Figure 15-8. Data Transfer Sequences for Master/Slave Transmit/Receive Modes

START

Address

ACK

TX Data1

TXBE=0

MRW=0

MAST=1

TXIF=1

TXBE=1

NAKIF=1

MAST=0

TXBE=1

(a) Master Transmit Mode

(b) Master Receive Mode

TXIF=1

TXBE=0

ACK

TX DataN

NAK

STOP

TXIF=1

TXBE=1

START

Address

ACK

RX Data1

RXBF=0

MAST=1

TXBE=0

RXBF=1

RXIF=1

NAKIF=1

MAST=0

RXIF=1

RXBF=1

ACK

RX DataN

NAK

STOP

START

Address

ACK

TX Data1

TXBE=1

RXBF=0

NAKIF=1

TXBE=0

TXBE=1

(d) Slave Receive Mode

TXIF=1

ACK

TX DataN

NAK

STOP

RXBF=1

RXIF=1

MATCH=1

SRW=1

TXIF=1

TXBE=1

START

Address

ACK

RX Data1

RXBF=1

RXIF=1

RXBF=1

ACK

RX DataN

NAK

STOP

TXBE=0

RXBF=0

RXBF=1

RXIF=1

MATCH=1

SRW=0

Data1 → DDRR

DataN → DDRR

Data1 → DDTR

Data2 → DDTR

DataN+2 → DDTR

Data1 → DDTR

Data2 → DDTR

Data3 → DDTR

DataN+2 → DDTR

(dummy data → DDTR)

MRW=1

Data1 → DDRR

DataN → DDRR

KEY: shaded data packets indicate a transmit by the MCU’s DDC module

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