M68HC08 datasheet(209/288 Pages) FREESCALE

209 / 288 page

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

Sync Processor

209

Data Sheet — MC68HC908BD48

Section 16. Sync Processor

16.1 Contents

16.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

16.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

16.4

I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

16.5

Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

16.5.1

Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

16.5.1.1

Hsync Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . 214

16.5.1.2

Vsync Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . 214

16.5.1.3

Composite Sync Polarity Detection . . . . . . . . . . . . . . . . 214

16.5.2

Sync Signal Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

16.5.3

Polarity Controlled HSYNCO and VSYNCO Outputs . . . . . 215

16.5.4

Clamp Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

16.5.5

Low Vertical Frequency Detect . . . . . . . . . . . . . . . . . . . . . 217

16.6

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

16.6.1

Sync Processor Control & Status Register (SPCSR) . . . . . 217

16.6.2

Sync Processor Input/Output Control Register (SPIOCR) . 219

16.6.3

Vertical Frequency Registers (VFRs) . . . . . . . . . . . . . . . . . 221

16.6.4

Hsync Frequency Registers (HFRs). . . . . . . . . . . . . . . . . . 223

16.6.5

Sync Processor Control Register 1 (SPCR1). . . . . . . . . . . 225

16.6.6

H&V Sync Output Control Register (HVOCR) . . . . . . . . . . 226

16.7

System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

16.2 Introduction

The Sync Processor is designed to detect and process sync signals

inside a digital monitor system — from separated Hsync and Vsync

inputs, or from composite sync inputs such as Sync-On-Green (SOG).

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