M68HC08 datasheet(204/288 Pages) FREESCALE

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DDC12AB Interface

Data Sheet

MC68HC908BD48 — Rev. 2.1

204

DDC12AB Interface

Freescale Semiconductor

RXBF — DDC Receive Buffer Full

This flag indicates the status of the data receive register (DDRR).

When the CPU reads the data from the DDRR, the RXBF flag will be

cleared. RXBF is set when DDRR is full by a transfer of data from the

input circuit to the DDRR. Reset clears this bit.

1 = Data receive register full

0 = Data receive register empty

15.6.6 DDC Data Transmit Register (DDTR)

When the DDC module is enabled, DEN = 1, data written into this

In slave mode, the data in DDTR will be transferred to the output circuit

when:

•

the module detects a matched calling address (MATCH = 1), with

the calling master requesting data (SRW = 1); or

•

the previous data in the output circuit has be transmitted and the

receiving master returns an acknowledge bit, indicated by a

received acknowledge bit (RXAK = 0).

If the calling master does not return an acknowledge bit (RXAK = 1), the

module will release the SDA line for master to generate a "stop" or

"repeated start" condition. The data in the DDTR will not be transferred

to the output circuit until the next calling from a master. The transmit

buffer empty flag remains cleared (TXBE = 0).

In master mode, the data in DDTR will be transferred to the output circuit

when:

Address:

$001A

Bit 7

654321

Bit 0

Read:

DTD7

DTD6

DTD5

DTD4

DTD3

DTD2

DTD1

DTD0

Write:

Reset:

11111111

Figure 15-6. DDC Data Transmit Register (DDTR)

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