M68HC08 datasheet(200/288 Pages) FREESCALE

200 / 288 page

DDC12AB Interface

Data Sheet

MC68HC908BD48 — Rev. 2.1

200

DDC12AB Interface

Freescale Semiconductor

NAKIF — No Acknowledge Interrupt Flag

This flag is only set in master mode (MAST = 1) when there is no

acknowledge bit detected after one data byte or calling address is

transferred. This flag also clears MAST. NAKIF generates an interrupt

request to CPU if the DIEN bit in DCR is also set. This bit is cleared

by writing "0" to it or by reset.

1 = No acknowledge bit detected

0 = Acknowledge bit detected

BB — Bus Busy Flag

This flag is set after a start condition is detected (bus busy), and is

cleared when a stop condition (bus idle) is detected or the DDC is

disabled. Reset clears this bit.

1 = Start condition detected

0 = Stop condition detected or DDC is disabled

MAST — Master Control Bit

This bit is set to initiate a master mode transfer. In master mode, the

module generates a start condition to the SDA and SCL lines,

followed by sending the calling address stored in DADR.

When the MAST bit is cleared by NAKIF set (no acknowledge) or by

software, the module generates the stop condition to the lines after

the current byte is transmitted.

If an arbitration loss occurs (ALIF = 1), the module reverts to slave

mode by clearing MAST, and releasing SDA and SCL lines

immediately.

This bit is cleared by writing "0" to it or by reset.

1 = Master mode operation

0 = Slave mode operation

MRW — Master Read/Write

This bit will be transmitted out as bit 0 of the calling address when the

module sets the MAST bit to enter master mode. The MRW bit

determines the transfer direction of the data bytes that follows. When

it is "1", the module is in master receive mode. When it is "0", the

module is in master transmit mode. Reset clears this bit.

1 = Master mode receive

0 = Master mode transmit

M68HC08 Datasheet(PDF) 200 Page - Freescale Semiconductor, Inc