M68HC08 datasheet(199/288 Pages) FREESCALE

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DDC12AB Interface

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

DDC12AB Interface

199

SCLIEN — SCL Interrupt Enable

When this bit is set, the SCLIF flag is enabled to generate an interrupt

request to the CPU. When SCLIEN is cleared, SCLIF is prevented

from generating an interrupt request. Reset clears this bit.

1 = SCLIF bit set will generate interrupt request to CPU

0 = SCLIF bit set will not generate interrupt request to CPU

DDC1EN — DDC1 Protocol Enable

This bit is set to enable DDC1 protocol. The DDC1 protocol will use

the Vsync input (from sync processor) as the master clock input to the

DDC module. Vsync rising-edge will continuously clock out the data

to the output circuit. No calling address comparison is performed. The

SRW bit in DDC status register (DSR) will always read as "1". Reset

clears this bit.

1 = DDC1 protocol enabled

0 = DDC1 protocol disabled

15.6.4 DDC Master Control Register (DMCR)

ALIF — DDC Arbitration Lost Interrupt Flag

This flag is set when software attempt to set MAST but the BB has

been set by detecting the start condition on the lines or when the DDC

is transmitting a "1" to SDA line but detected a "0" from SDA line in

master mode – an arbitration loss. This bit generates an interrupt

request to the CPU if the DIEN bit in DCR is also set. This bit is

cleared by writing "0" to it or by reset.

1 = Lost arbitration in master mode

0 = No arbitration lost

Address:

$0016

Bit 7

654321

Bit 0

Read:

ALIF

NAKIF

MAST

MRW

BR2

BR1

BR0

Write:

Reset:

00000000

Figure 15-4. DDC Master Control Register (DMCR)

M68HC08 Datasheet(PDF) 199 Page - Freescale Semiconductor, Inc

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