M68HC08 datasheet(198/288 Pages) FREESCALE

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DDC12AB Interface

Data Sheet

MC68HC908BD48 — Rev. 2.1

198

DDC12AB Interface

Freescale Semiconductor

15.6.3 DDC Control Register (DCR)

DEN — DDC Enable

This bit is set to enable the DDC module. When DEN = 0, module is

disabled and all flags will restore to its power-on default states. Reset

clears this bit.

1 = DDC module enabled

0 = DDC module disabled

DIEN — DDC Interrupt Enable

When this bit is set, the TXIF, RXIF, ALIF, and NAKIF flags are

enabled to generate an interrupt request to the CPU. When DIEN is

cleared, the these flags are prevented from generating an interrupt

request. Reset clears this bit.

1 = TXIF, RXIF, ALIF, and/or NAKIF bit set will generate interrupt

request to CPU

0 = TXIF, RXIF, ALIF, and/or NAKIF bit set will not generate

interrupt request to CPU

TXAK — Transmit Acknowledge Enable

This bit is set to disable the DDC from sending out an acknowledge

signal to the bus at the 9th clock bit after receiving 8 data bits. When

TXAK is cleared, an acknowledge signal will be sent at the 9th clock

bit. Reset clears this bit.

1 = DDC does not send acknowledge signals at 9th clock bit

0 = DDC sends acknowledge signal at 9th clock bit

Address:

$0018

Bit 7

654321

Bit 0

Read:

DEN

DIEN

TXAK

SCLIEN DDC1EN

Write:

Reset:

00000000

= Unimplemented

Figure 15-3. DDC Control Register (DCR)

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