M68HC08 datasheet(196/288 Pages) FREESCALE

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DDC12AB Interface

Data Sheet

MC68HC908BD48 — Rev. 2.1

196

DDC12AB Interface

Freescale Semiconductor

15.5 DDC Protocols

In DDC1 protocol communication, the module is in transmit mode. The

data written to the transmit register is continuously clocked out to the

SDA line by the rising edge of the Vsync input signal. During DDC1

communication, a falling transition on the SCL line can be detected to

generate an interrupt to the CPU for mode switching.

In DDC2AB protocol communication, the module can be either in

transmit mode or in receive mode, controlled by the calling master.

In DDC2 protocol communication, the module will act as a standard IIC

module, able to act as a master or a slave device.

15.6 Registers

Seven registers are associated with the DDC module, they outlined in

the following sections.

15.6.1 DDC Address Register (DADR)

DAD[7:1] — DDC Address

These 7 bits can be the DDC2 interface’s own specific slave address

in slave mode or the calling address when in master mode. Reset sets

a default value of $A0.

Address:

$0017

Bit 7

654321

Bit 0

Read:

DAD7

DAD6

DAD5

DAD4

DAD3

DAD2

DAD1

EXTAD

Write:

Reset:

10100000

Figure 15-1. DDC Address Register (DADR)

M68HC08 Datasheet(PDF) 196 Page - Freescale Semiconductor, Inc

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