M68HC08 datasheet(194/288 Pages) FREESCALE

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DDC12AB Interface

Data Sheet

MC68HC908BD48 — Rev. 2.1

194

DDC12AB Interface

Freescale Semiconductor

This DDC12AB module uses the DDCSCL clock line and the DDCSDA

data line to communicate with external DDC host or IIC interface. These

two pins are shared with port pins PTD3 and PTD2 respectively. The

outputs of DDCSDA and DDCSCL pins are open-drain type — no

clamping diode is connected between the pin and internal VDD. The

maximum data rate typically is 100k-bps. The maximum communication

length and the number of devices that can be connected are limited by

a maximum bus capacitance of 400pF.

15.3 Features

•

DDC1 hardware

•

Compatibility with multi-master IIC bus standard

•

Software controllable acknowledge bit generation

•

Interrupt driven byte by byte data transfer

•

Calling address identification interrupt

•

Auto detection of R/W bit and switching of transmit or receive

mode

•

Detection of START, repeated START, and STOP signals

•

Auto generation of START and STOP condition in master mode

•

Arbitration loss detection and No-ACK awareness in master mode

•

8 selectable baud rate master clocks

•

Automatic recognition of the received acknowledge bit

15.4 I/O Pins

The DDC12AB module uses two I/O pins, shared with standard port I/O

pins. The full name of the DDC12AB I/O pins are listed in Table 15-1

The generic pin name appear in the text that follows.

Table 15-1. Pin Name Conventions

DDC12AB

Generic Pin Names:

Full MCU Pin Names:

Pin Selected for

DDC Function By:

SDA

PTD2/DDCSDA

DDCDATE bit in PDCR ($0049)

SCL

PTD3/DDCSCL

DDCSCLE bit in PDCR ($0049)

M68HC08 Datasheet(PDF) 194 Page - Freescale Semiconductor, Inc

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