M68HC08 datasheet(190/288 Pages) FREESCALE

190 / 288 page

Multi-Master IIC Interface (MMIIC)

Data Sheet

MC68HC908BD48 — Rev. 2.1

190

Multi-Master IIC Interface (MMIIC)

Freescale Semiconductor

•

the calling address from the master when the address match flag

is set (MMATCH = 1); or

•

the last data received when MMATCH = 0.

In master mode, the data in the MMDRR is:

•

the last data received.

When the MMDRR is read by the CPU, the receive buffer full flag is

cleared (MMRXBF = 0), and the next received data is loaded to the

MMDRR. Each time when new data is loaded to the MMDRR, the

MMRXIF interrupt flag is set, indicating that new data is available in

MMDRR.

The sequence of events for slave receive and master receive are

illustrated in Figure 14-7.

14.6 Programming Considerations

When the MMIIC module detects an arbitration loss in master mode, it

will release both SDA and SCL lines immediately. But if there are no

further STOP conditions detected, the module will hang up. Therefore, it

is recommended to have time-out software to recover from such ill

condition. The software can start the time-out counter by looking at the

MMBB (Bus Busy) flag in the MIMCR and reset the counter on the

completion of one byte transmission. If a time-out occur, software can

clear the MMEN bit (disable MMIIC module) to release the bus, and

hence clearing the MMBB flag. This is the only way to clear the MMBB

flag by software if the module hangs up due to a no STOP condition

received. The MMIIC can resume operation again by setting the MMEN

bit.

M68HC08 Datasheet(PDF) 190 Page - Freescale Semiconductor, Inc