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M68HC08 Datasheet(PDF) 189 Page - Freescale Semiconductor, Inc |
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M68HC08 Datasheet(HTML) 189 Page - Freescale Semiconductor, Inc |
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189 / 288 page ![]() Multi-Master IIC Interface (MMIIC) MC68HC908BD48 — Rev. 2.1 Data Sheet Freescale Semiconductor Multi-Master IIC Interface (MMIIC) 189 If the calling master does not return an acknowledge bit (MMRXAK = 1), the module will release the SDA line for master to generate a "stop" or "repeated start" condition. The data in the MMDTR will not be transferred to the output circuit until the next calling from a master. The transmit buffer empty flag remains cleared (MMTXBE = 0). In master mode, the data in MMDTR will be transferred to the output circuit when: • the module receives an acknowledge bit (MMRXAK = 0), after setting master transmit mode (MMRW = 0), and the calling address has been transmitted; or • the previous data in the output circuit has be transmitted and the receiving slave returns an acknowledge bit, indicated by a received acknowledge bit (MMRXAK = 0). If the slave does not return an acknowledge bit (MMRXAK = 1), the master will generate a "stop" or "repeated start" condition. The data in the MMDTR will not be transferred to the output circuit. The transmit buffer empty flag remains cleared (MMTXBE = 0). The sequence of events for slave transmit and master transmit are illustrated in Figure 14-7. 14.5.6 Multi-Master IIC Data Receive Register (MMDRR) When the MMIIC module is enabled, MMEN = 1, data in this read-only register depends on whether module is in master or slave mode. In slave mode, the data in MMDRR is: Address: $004F Bit 7 654321 Bit 0 Read: MMRD7 MMRD6 MMRD5 MMRD4 MMRD3 MMRD2 MMRD1 MMRD0 Write: Reset: 00000000 = Unimplemented Figure 14-6. Multi-Master IIC Data Receive Register (MMDRR) |
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