M68HC08 datasheet(186/288 Pages) FREESCALE

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Multi-Master IIC Interface (MMIIC)

Data Sheet

MC68HC908BD48 — Rev. 2.1

186

Multi-Master IIC Interface (MMIIC)

Freescale Semiconductor

14.5.4 Multi-Master IIC Status Register (MMSR)

MMRXIF — Multi-Master IIC Receive Interrupt Flag

This flag is set after the data receive register (MMDRR) is loaded with

a new received data. Once the MMDRR is loaded with received data,

no more received data can be loaded to the MMDRR register until the

CPU reads the data from the MMDRR to clear MMRXBF flag.

MMRXIF generates an interrupt request to CPU if the MMIEN bit in

MMCR is also set. This bit is cleared by writing "0" to it or by reset; or

when the MMEN = 0.

1 = New data in data receive register (MMDRR)

0 = No data received

Table 14-3. Baud Rate Select

MMBR2

MMBR1

MMBR0

Baud Rate

000

750k

001

375k

187.5k

011

93.75k

100

46.875k

101

23.437k

110

11.719k

5.859k

NOTE:

CPU bus clock is external clock ÷ 4 = 6MHz

Address:

$004D

Bit 7

654321

Bit 0

Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK

MMTXBE MMRXBF

Write:

Reset:

00001010

= Unimplemented

Figure 14-4. Multi-Master IIC Status Register (MMSR)

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