M68HC08 datasheet(185/288 Pages) FREESCALE

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Multi-Master IIC Interface (MMIIC)

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

Multi-Master IIC Interface (MMIIC)

185

MMAST — Master Control Bit

This bit is set to initiate a master mode transfer. In master mode, the

module generates a start condition to the SDA and SCL lines,

followed by sending the calling address stored in MMADR.

When the MMAST bit is cleared by MMNAKIF set (no acknowledge)

or by software, the module generates the stop condition to the lines

after the current byte is transmitted.

If an arbitration loss occurs (MMALIF = 1), the module reverts to slave

mode by clearing MMAST, and releasing SDA and SCL lines

immediately.

This bit is cleared by writing "0" to it or by reset.

1 = Master mode operation

0 = Slave mode operation

MMRW — Master Read/Write

This bit will be transmitted out as bit 0 of the calling address when the

module sets the MMAST bit to enter master mode. The MMRW bit

determines the transfer direction of the data bytes that follows. When

it is "1", the module is in master receive mode. When it is "0", the

module is in master transmit mode. Reset clears this bit.

1 = Master mode receive

0 = Master mode transmit

MMBR2–MMBR0 — Baud Rate Select

These three bits select one of eight clock rates as the master clock

when the module is in master mode.

Since this master clock is derived the CPU bus clock, the user

program should not execute the WAIT instruction when the MMIIC

module in master mode. This will cause the SDA and SCL lines to

hang, as the WAIT instruction places the MCU in WAIT mode, with

CPU clock is halted. These bits are cleared upon reset. (See Table

14-3 . Baud Rate Select.)

M68HC08 Datasheet(PDF) 185 Page - Freescale Semiconductor, Inc