M68HC08 datasheet(183/288 Pages) FREESCALE

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Multi-Master IIC Interface (MMIIC)

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

Multi-Master IIC Interface (MMIIC)

183

14.5.2 Multi-Master IIC Control Register (MMCR)

MMEN — Multi-Master IIC Enable

This bit is set to enable the Multi-master IIC module. When

MMEN = 0, module is disabled and all flags will restore to its power-

on default states. Reset clears this bit.

1 = MMIIC module enabled

0 = MMIIC module disabled

MMIEN — Multi-Master IIC Interrupt Enable

When this bit is set, the MMTXIF, MMRXIF, MMALIF, and MMNAKIF

flags are enabled to generate an interrupt request to the CPU. When

MMIEN is cleared, the these flags are prevented from generating an

interrupt request. Reset clears this bit.

1 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will

generate interrupt request to CPU

0 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will not

generate interrupt request to CPU

MMTXAK — Transmit Acknowledge Enable

This bit is set to disable the MMIIC from sending out an acknowledge

signal to the bus at the 9th clock bit after receiving 8 data bits. When

MMTXAK is cleared, an acknowledge signal will be sent at the 9th

clock bit. Reset clears this bit.

1 = MMIIC does not send acknowledge signals at 9th clock bit

0 = MMIIC sends acknowledge signal at 9th clock bit

Address:

$004C

Bit 7

654321

Bit 0

Read:

MMEN

MMIEN

MMTXAK

000

Write:

Reset:

00000000

= Unimplemented

Figure 14-2. Multi-Master IIC Control Register (MMCR)

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