M68HC08 datasheet(180/288 Pages) FREESCALE

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Multi-Master IIC Interface (MMIIC)

Data Sheet

MC68HC908BD48 — Rev. 2.1

180

Multi-Master IIC Interface (MMIIC)

Freescale Semiconductor

This Multi-master IIC module uses the IICSCL clock line and the IICSDA

data line to communicate with external DDC host or IIC interface. These

two pins are shared with port pins PTD5 and PTD6 respectively. The

outputs of IICSDA and IICSCL pins are open-drain type — no clamping

diode is connected between the pin and internal VDD. The maximum

data rate typically is 750k-bps. The maximum communication length and

the number of devices that can be connected are limited by a maximum

bus capacitance of 400pF.

14.3 Features

•

Compatibility with multi-master IIC bus standard

•

Software controllable acknowledge bit generation

•

Interrupt driven byte by byte data transfer

•

Calling address identification interrupt

•

Auto detection of R/W bit and switching of transmit or receive

mode

•

Detection of START, repeated START, and STOP signals

•

Auto generation of START and STOP condition in master mode

•

Arbitration loss detection and No-ACK awareness in master mode

•

8 selectable baud rate master clocks

•

Automatic recognition of the received acknowledge bit

14.4 I/O Pins

The MMIIC module uses two I/O pins, shared with standard port I/O pins.

The full name of the MMIIC I/O pins are listed in Table 14-1

. The generic

pin name appear in the text that follows.

Table 14-1. Pin Name Conventions

MMIIC

Generic Pin Names:

Full MCU Pin Names:

Pin Selected for

IIC Function By:

SDA

PTD6/IICSDA

IICDATE bit in PDCR ($0049)

SCL

PTD5/IICSCL

IICSCLE bit in PDCR ($0049)

M68HC08 Datasheet(PDF) 180 Page - Freescale Semiconductor, Inc

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