M68HC08 datasheet(169/288 Pages) FREESCALE

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Universal Serial Bus Module (USB)

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

Universal Serial Bus Module (USB)

169

13.5.3 USB Interrupt Register 1 (UIR1)

TXD1F — Endpoint 1/2 Data Buffer Transmit Flag

The flag is set after the data stored in endpoint 1/2 transmit buffer has

been sent and ACK handshake packet from host is received.

Software must clear this flag by writing a logic 1 to TXD1FR bit after

the data is ready in the transmit buffer to enable the next data packet

transmission when TX1E is enabled. Reset clears this bit.

1 = Transmit on endpoint 1/2 has occurred

0 = Transmit on endpoint 1/2 has not occurred

TXD1IE — Transmit Buffer Interrupt Enable

When this bit is set, the TXD1F flag is enabled to generate an interrupt

request to the CPU. When TXD1IE is cleared, the TXD1F flag is

prevented from generating an interrupt request to the CPU. Reset

clears this bit.

1 = TXD1F bit set will generate interrupt request to CPU

0 = TXD1F bit set does not generate interrupt request to CPU

RESUMF — Resume Flag

This flag is set if the transaction from idle state to non-idle state is

detected while in suspend mode (SUSPND = 1). An interrupt will be

generated to wake up CPU to indicate a resume signalling from host

and software will clear SUSPND bit and exit from suspend mode.

USB reset signals cannot be detected while in suspend mode until

SUSPND bit is cleared. The RESUMF interrupt service routine is

generated by SE0 to wake up the USB module. This bit can be

cleared by writing "1" to RESUMFR bit. Reset clears this bit.

1 = USB bus activity detected while in suspend mode

0 = If in suspend mode, no USB bus activity has been detected

Address:

$002E

Bit 7

654321

Bit 0

Read: TXD1F

TXD1IE

RESUMF

00000

Write:

RESUMFR

TBEFR

RBFFR

TXD1FR

EOPFR

Reset:

00000000

Figure 13-3. USB Interrupt Register 1 (UIR1)

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