TDA9321 datasheet(10/44 Pages) PHILIPS

10 / 44 page

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

RGB switch and matrix

The IC has 2 RGB inputs with fast switching. The switching

of the various sourcing is controlled via the I2C-bus and the

condition of the switch inputs can be read from the I2C-bus

status bytes. If the RGB signals are not synchronous with

the selected decoder input signal, an external clamp pulse

has to be supplied to the HA/CLP input. The IC must be set

in this mode via the I2C-bus. In that case the vertical pulse

is suppressed by switching the VA output in a

high-impedance off-state.

When an external RGB signal is mixed with the internal

YUV signal it is necessary to switch-off the PALplus

demodulation. To detect the presence of a fast blanking a

circuit is added which forces bits MACP and HD to zero if

a blanking pulse is detected in 2 consecutive lines. This

system is chosen to prevent switching-off at every spike

which is detected on the fast blanking input.

The IC has the possibility to use the RGB1 input as YUV

input. This function can be enabled by means of bit YUV in

subaddress 0A (D3). When switched to the YUV input the

input signals must have the same amplitude and polarity

as the YUV output signals. The Y signal has to be supplied

to the GI1 input, the U signal to the BI1 input and the

V signal to the RI1 input.

Synchronization circuit

The sync separator is preceded by a controlled amplifier

which adjusts the sync pulse amplitude to a fixed level.

These pulses are fed to the slicing stage which operates at

50% of the amplitude. The separated sync pulses are fed

to the phase detector and to the coincidence detector. This

coincidence detector is used to detect whether the line

oscillator is synchronized and can also be used for

transmitter identification. This circuit can be made less

sensitive with bit STM. This mode can be used during

search tuning to avoid the tuning system stopping at very

weak input signals. The PLL has a very high statical

steepness so that the phase of the picture is independent

of the line frequency.

For the horizontal output pulse 2 conditions are possible:

• An HA pulse which has a phase and width which is

identical to the incoming horizontal sync pulse

• A clamp pulse (CLP) which has a phase and width which

is identical to the clamp pulse in the sandcastle pulse.

The HA/CLP signal is generated by means of an oscillator

which is running at a frequency of 440

× f

hor. Its frequency

is divided by 440 to lock the first loop to the incoming

signal. The time constant of the loop can be forced by the

I2C-bus (fast or slow).

If required the IC can select the time constant depending

on the noise content of the incoming video signal.

The free-running frequency of the oscillator is determined

by a digital control circuit which is locked to the reference

signal of the colour decoder. When the IC is switched on

the HA/CLP is suppressed and the oscillator is calibrated

as soon as all subaddress bytes have been sent. When the

frequency of the oscillator is correct the HA/CLP signal is

switched on again. When the coincidence detector

indicates an out-of-lock situation the calibration procedure

is repeated.

The VA pulse is obtained via a vertical count-down circuit.

The count-down circuit has various windows depending on

the incoming signal (50 or 60 Hz standard or

non-standard). The count-down circuit can be forced in

various modes via the I2C-bus. To obtain short switching

times of the count-down circuit during a channel change

the divider can be forced in the search window by means

of bit NCIN.

I2C-BUS SPECIFICATION

The slave address of the IC is given in Table 1. Bit A1 is

controlled via pin AS. When pin AS is connected to

pin GND2 it is at logic 0 and when connected to VP2 it is at

logic 1. When pin AS is left open-circuit it is connected to

ground via an internal pull-up resistor. The circuit operates

at clock frequencies of up to 400 kHz.

Table 1

Slave address bits

Start-up procedure

Read the status bytes until bit POR = 0 and send all

subaddress bytes. It is advised to check the I2C-bus

transmission by reading the output status bits SXA

to SXD. This ensures a good operation of the calibration

system of the horizontal oscillator. The horizontal output

signal is switched on when the oscillator is calibrated.

Each time before the data in the IC is refreshed, the status

bytes must be read. If bit POR = 1, then the procedure

mentioned above must be carried out to restart the IC.

When this procedure is not carried out the horizontal

frequency may be incorrect after power-up or after a power

dip.

The valid subaddresses are 00 to 0E. Subaddresses

FE and FF are reserved for test purposes. Auto-increment

mode is available for the subaddresses.

R/W

10001

1/0

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