TDA9321 datasheet(13/44 Pages) PHILIPS

13 / 44 page

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

Table 15 Phase 1 (

ϕ1) time constant; see also Table 57

Table 16 Video ident mode

Table 17 Synchronization mode

Table 18 Video ident mode

FOA

FOB

MODE

normal

slow

slow or fast

fast

VIM

MODE

ident coupled to internal CVBS (pin 14)

ident coupled to selected CVBS

POC

MODE

active

not active

VID

VIDEO IDENT MODE

1 loop switched-on and off

not active

Table 19 Blanked sync on pin YO

Note

1. Except for PALplus with black set-up.

Table 20 Condition of horizontal output

Table 21 Enable ‘Macrovision/subtitle’ gating

Table 22 Vertical divider mode

BSY

CONDITIONS

unblanked sync; note 1

blanked sync

CONDITIONS

clamp pulse available on pin HA/CLP

horizontal pulse available on pin HA/CLP

EMG

MODE

disable gating

enable gating

NCIN

VERTICAL DIVIDER MODE

normal operation

switched to search window

Table 23 Video switch control

ECMB(1)

DEC3

DEC2

DEC1

DEC0

SELECTED SIGNAL

SIGNAL TO COMB

0000

X(2)

CVBSint

00010

CVBS1

00011

CVBS2

00100

CVBS3

00101

Y3/C3

Y3 + C3

00110

CVBS4

00111

Y4/C4

Y4 + C4

01100

AUTO Y3/C3; note 3

CVBS3 or Y3 + C3

01110

AUTO Y4/C4; note 3

CVBS4 or Y4 + C4

1000

X(2)

YCF/CCF

CVBSint

10010

YCF/CCF

CVBS1

10011

YCF/CCF

CVBS2

10100

YCF/CCF

CVBS3

10110

YCF/CCF

CVBS4

11100

AUTO COMB3; note 4

CVBS3 or Y3 + C3

11110

AUTO COMB4; note 4

CVBS4 or Y4 + C4

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