TDA9321 datasheet(31/44 Pages) PHILIPS

31 / 44 page

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

Notes to the characteristics

1. The two supply pins VP1 and VP2 must be decoupled separately but they must be connected to a single power supply

to avoid too big differences between them.

2. On set AGC.

3. This parameter is not tested during production and is just given as application information for the designer of the

television receiver.

4. Loop filter bandwidth Blpf = 60 kHz (natural frequency fn = 15 kHz; damping factor d = 2; calculated with top sync

level as fPLL input signal level). LC-VCO circuit between pins 7 and 8: Q0 = 60; Cint = 30 pF.

5. The optimum temperature stability of the PLL can be obtained when a TOKO coil as given in Table 55 is applied.

6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix

batches which are made in the pilot production period.

7. Measured at 10 mV (RMS value) top sync input signal.

8. So called projected zero point, i.e. with switched demodulator.

9. Measured in accordance with the test line given in Fig.5. For the differential phase test the peak white setting is

reduced to 87%.

The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and

smallest value relative to the subcarrier amplitude at blanking level.

The differential phase is defined as the difference in degrees between the largest and smallest phase angle.

10. This figure is valid for the complete video signal amplitude (peak white-to-black). See Fig.6.

11. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal).

delay between mid sync of input

and start of clamping pulse

note 30

3.0

3.2

3.4

µs

I2C-BUS CONTROL

SCL AND SDA INPUTS/OUTPUTS (PINS SCL AND SDA)

input voltage range

−

5.5

VIL

LOW-level input voltage

−−

1.5

VIH

HIGH-level input voltage

3.5

−−

IIL

LOW-level input current

VIL =0V

−−

−10

µA

IIH

HIGH-level input current

VIH = 5.5 V

−−

µA

VOL(SDA)

LOW-level output voltage on

pin SDA

IOL(SDA) =3mA

−−

0.4

SW0 AND SW1 OUTPUTS (PINS SW0 AND SW1); note 36

VOH

HIGH-level output voltage

4.0

5.0

5.5

VOL

LOW-level output voltage

−

0.2

0.4

IO(sink)

output sink current

−−

IO(source)

output source current

−−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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