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TDA9321 Datasheet(PDF) 33 Page - NXP Semiconductors |
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TDA9321 Datasheet(HTML) 33 Page - NXP Semiconductors |
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33 / 44 page ![]() 1998 Dec 16 33 Philips Semiconductors Preliminary specification I2C-bus controlled TV input processor TDA9321H 27. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9922 520 with a series capacitance Cs = 18 pF. The oscillator circuit is rather insensitive to the spurious responses of the crystal. As long as the resonance resistance of the third overtone is higher than that of the fundamental frequency the oscillator will operate at the correct frequency. The typical crystal parameters for the crystal series are: a) Load resonance frequencies fL: 4.433619, 3.579545, 3.582056 and 3.575611 MHz; Cs = 20 pF. b) Motional capacitance Cmot = 20.6 fF (4.43 MHz crystal) or Cmot = 14.7 fF (3.58 MHz crystal). c) Parallel capacitance Cp = 5.0 pF. The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and therefore the figures regarding catching range are only valid for the specified crystal series. In this figure tolerances of the crystal with respect to the nominal frequency, motional capacitance and ageing have been taken into account and have been counted for gaussic addition. Whenever different typical crystal parameters are used the following equation might be helpful for calculating the impact on the tuning capabilities: Detuning range = The resulting detuning range should be corrected for temperature shift and supply voltage deviation of both the IC and the crystal. To guarantee a catching range of ±300 Hz on 4.43 MHz the minimum motional capacitance of the crystal must have a value 13.2 fF or higher. For a catching range of 250 Hz with the 3.58 MHz crystal the minimum motional capacitance must have a value of 9 fF. The actual series capacitance in the application should be Cs = 18 pF to account for parasitic capacitances on-chip and off-chip. 28. The hue control is active for NTSC on the demodulated colour difference signals and for PALplus on the demodulated helper signal. 29. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance band-pass filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz. 30. This delay is partially caused by the low-pass filter at the sync separator input. 31. The internal luminance signal (signal which is derived from the incoming CVBS or Y/C signals) has a separate gain control setting (controlled by the I2C-bus bits GAI1 and GAI0 and with a gain variation between −1 and +2 dB) which can be used to get an optimal input signal amplitude for the feature box. 32. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 4 V (peak-to-peak value). 33. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition and the condition of the I2C-bus. Therefore the circuit contains a noise detector and the time constant is switched to the slow mode when too much noise is present in the signal. In the fast mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be automatic or overruled by the I2C-bus. The circuit contains a video identification circuit which is independent of the first control loop. This identification circuit can be used to close or open the first control loop when a video signal is present or not present on the input. This enables a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification circuit with the first control loop can be revoked via the I2C-bus. C mot 1 C p C s ------- + 2 -------------------------- |
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