TDA9321 datasheet(28/44 Pages) PHILIPS

28 / 44 page

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

output impedance

−−

250

Ω

output DC voltage level

black level

2.8

3.0

3.2

BRGB(−3dB)

−3 dB bandwidth of the RGB

switch circuit

−−

MHz

S/N

signal-to-noise ratio

fi = 0 to 5 MHz

−

Vsu(bl)

black set-up amplitude

bit MACP = 1 or

bit HD = 1

190

200

210

tW(su)(bl)

black set-up pulse width

−

52.8

−µs

delay between mid sync at input

and black set-up

note 30

−

8.8

−µs

Voffset

offset voltage

Ybl to re-inserted black

−−

G(Y/CVBS-YO)

gain from internal Y/CVBS

to YO

1.35

1.43

1.50

bit MACP = 1 or

bit HD = 1

1.08

1.14

1.20

UO AND VO SIGNAL OUTPUTS (PINS UO AND VO)

Vo(VO)(p-p)

output voltage on pin VO

(peak-to-peak value)

standard EBU colour bar

0.88

1.05

1.25

Vo(UO)(p-p)

output voltage on pin UO

(peak-to-peak value)

standard EBU colour bar

1.12

1.33

1.58

output impedance

−−

250

Ω

output DC voltage level

2.2

2.4

2.6

∆V

bl(YUV-RGB)

difference in black level

between YUV and RGB mode

−−

COLOUR MATRIX FROM RGB TO YUV

gain

from RI to YO

0.40

0.43

0.46

from GI to YO

0.79

0.84

0.90

from BI to YO

0.15

0.16

0.17

from RI to UO

0.40

0.43

0.46

from GI to UO

0.79

0.84

0.90

from BI to UO

1.19

1.27

1.35

from RI to VO

0.94

1.00

1.07

from GI to VO

0.79

0.84

0.90

from BI to VO

0.15

0.16

0.17

Horizontal and vertical synchronization

SYNC VIDEO INPUTS

Vsync

sync pulse amplitude

note 3

300

350

SLhor

slicing level for horizontal sync

note 32

SLvert

slicing level for vertical sync

note 32

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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