AX88796ALF datasheet(28/68 Pages) ASIX

28 / 68 page

AX88796ALF

3-in-1 Local Bus Fast Ethernet Controller

4.2.2

Packet Transmission

The Local DMA Read is also used during transmission of a packet. Three registers control the DMA transfer

during transmission, a Transmit Page Start Address Register (TPSR) and the Transmit Byte Count Registers

(TBCR0, 1). When the AX88796A receives a command to transmit the packet pointed to by these registers,

buffer memory data will be moved into the FIFO as required during transmission. The AX88796A Controller

will generate and append the preamble, synch and CRC fields.

TRANSMIT PACKET ASSEMBLY

The AX88796A requires a contiguous assembled packet with the format shown. The transmit byte count

includes the Destination Address, Source Address, Length Field and Data. It does not include preamble and

CRC. When transmitting data smaller than 46 bytes, the packet must be padded to a minimum size of 64 bytes.

The programmer is responsible for adding and stripping pad bytes. The packets are placed in the buffer RAM

by the system. System programs the AX88796A Core’s Remote DMA to move the data from the data port to

the RAM handshaking with system transfers loading the I/O data port.

The data transfer must be 16 bits (1 word) when in 16-bit mode, and 8 bits when the AX88796A Controller is

set in 8-bit mode. The data width is selected by setting the WTS bit in the Data Configuration Register and

setting the CPU[1:0] pins for ISA, 80186 or MC68K mode.

Destination Address

6 Bytes

Source Address

6 Bytes

Length / Type

2 Bytes

Data

(Pad if < 46 Bytes)

46 Bytes

Min.

General Transmit Packet Format

TRANSMISSION

Prior to transmission, the TPSR (Transmit Page Start Register) and TBCR0, TBCR1 (Transmit Byte Count

Registers) must be initialized. To initiate transmission of the packet the TXP bit in the Command Register is

set. The Transmit Status Register (TSR) is cleared and the AX88796A begins to prefetch transmit data from

memory. If the Interpacket Gap (IPG) has timed out the AX88796A will begin transmission.

CONDITIONS REQUIRED TO BEGIN TRANSMISSION

In order to transmit a packet, the following three conditions must be met:

1. The Interpacket Gap Timer has timed out.

2. At least one byte has entered the FIFO. (This indicates that the burst transfer has been started).

3. If a collision had been detected then before transmission the packet backoff time must have timed out.

AX88796ALF Datasheet(PDF) 28 Page - ASIX Electronics Corporation