| Electronic Components Datasheet Search |
|
AX88796ALF Datasheet(PDF) 44 Page - ASIX Electronics Corporation |
|
|
|||||||||||||||||||||||||||||
AX88796ALF Datasheet(HTML) 44 Page - ASIX Electronics Corporation |
|
44 / 68 page ![]() 44 AX88796ALF 3-in-1 Local Bus Fast Ethernet Controller Copyright © 2006-2013 ASIX Electronics Corporation. All rights reserved. 5.2.2 MR1 – Status Register Bit Descriptions FIELD TYPE DESCRIPTION 1.15 (T4ABLE) R 100Base-T4 Ability. This bit will always be a 0. 0: Not able. 1: Able. 1.14 (TXFULDUP) R 100Base-TX Full-Duplex Ability. This bit will always be a 1. 0: Not able. 1: Able. 1.13 (TXHAFDUP) R 100Base-TX Half-Duplex Ability. This bit will always be a 1. 0: Not able. 1: Able. 1.12 (ENFULDUP) R 10Base-T Full-Duplex Ability. This bit will always be a 1. 0: Not able. 1: Able. 1.11 (ENHAFDUP) R 10Base-T Half-Duplex Ability. This bit will always be a 1. 0: Not able. 1: Able. 1.10:7 (RESERVED) R Reserved. All bits will read as a 0. 1.6 (NO_PA_OK) R Suppress Preamble. 0 = AX88796A only accepts MII management frames without preamble suppressed. 1.5 (NWAYDONE) R Autonegotiation Complete. When this bit is a 1, it indicates the autonegotiation process has been completed. The contents of registers MR4, MR5, MR6, and MR7 are now valid. The default value is a 0. This bit is reset when autonegotiation is started. 1.4 (REM_FLT) R Remote Fault. When this bit is a 1, it indicates a remote fault has been detected. This bit will remain set until cleared by reading the register. The default is a 0. 1.3 (NWAYABLE) R Autonegotiation Ability. When this bit is a 1, it indicates the ability to perform autonegotiation. The value of this bit is always a 1. 1.2 (LSTAT_OK) R Link Status. When this bit is a 1, it indicates a valid link has been established. This bit has a latching function: a link failure will cause the bit to clear and stay cleared until it has been read via the management interface. 1.1 (JABBER) R Jabber Detect. This bit will be a 1 whenever a jabber condition is detected. It will remain set until it is read, and the jabber condition no longer exists. 1.0 (EXT_ABLE) R Extended Capability. This bit indicates that the PHY supports the extended register set (MR2 and beyond). It will always read a 1. 5.2.3 MR2, MR3 – Identification Registers (1 and 2) Bit Descriptions FIELD TYPE DESCRIPTION 2.15:0 (OUI[3:18]) R Organizationally Unique Identifier. The third through the twenty-fourth bit of the OUI assigned to the PHY manufacturer by the IEEE are to be placed in bits. 2.15:0 and 3.15:10. This value is programmable. Default value: 16’h003b. 3.15:10 (OUI[19:24]) R Organizationally Unique Identifier. The remaining 6 bits of the OUI. The value for bits 24:19 is programmable. Default value: 6’h06. 3.9:4 (MODEL[5:0]) R Model Number. 6-bit model number of the device. The model number is programmable. Default value: 6’h02. 3.3:0 (VERSION[3:0]) R Revision Number. The value of the present revision number. The version number is programmable. Default value: 4’h1. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |