AX88796ALF datasheet(43/68 Pages) ASIX

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AX88796ALF

3-in-1 Local Bus Fast Ethernet Controller

5.2 The Embedded PHY Registers

The MII management 16-bit register set implemented is as follows. And the following sub-section will describes each field

of the registers. The format for the “FIELD” descriptions is as follows: the first number is the register number, the second

number is the bit position in the register and the name of the instantiated pad is in capital letters. The format for the “TYPE”

descriptions is as follows: R = read, W = write, LH = latch high, NA = not applicable.

ADDRESS

NAME

DESCRIPTION

DEFAULT (Hex Code)

MR0

Control

3000h

MR1

Status

7849h

MR2

PHY Identifier 1

003Bh

MR3

PHY Identifier 2

1821h

MR4

Autonegotiation Advertisement

01E1h

MR5

Autonegotiation Link Partner Ability

0000

MR6

Autonegotiation Expansion

0000

TAB - 17

The Embedded PHY Registers

5.2.1 MR0 – Control Register Bit Descriptions

FIELD

TYPE

DESCRIPTION

0.15 (SW_RESET)

R/W

Reset. Setting this bit to a 1 will reset the PHY. All registers will be set to

their default state. This bit is self-clearing. The default is 0.

0.14 (LOOPBACK)

R/W

Loopback. When this bit is set to 1, no data transmission will take place on

the media. Any receive data will be ignored. The loopback signal path will

contain all circuitry up to, but not including, the PMD. The default value is a

0.13(SPEED100)

R/W

Speed Selection. The value of this bit reflects the current speed of operation

(1 = 100Mbits/s; 0 = 10Mbits/s). This bit will only affect operating speed

when the autonegotiation enable bit (register 0, bit 12) is disabled (0). This

bit is ignored when autonegotiation is enabled (register 0, bit 12). This bit is

ANDed with the SPEED_PIN signal.

0.12 (NWAY_ENA)

R/W

Autonegotiation Enable. The autonegotiation process will be enabled by

set-ting this bit to a 1. The default state is a 1.

0.11 (Reserved)

R/W

The default state is a 0. Always write 0.

0.10 (ISOLATE)

R/W

Isolate. When this bit is set to a 1, the MII outputs will be brought to the

high-impedance state. The default state is a 0.

0.9 (REDONWAY)

R/W

Restart Autonegotiation. Normally, the autonegotiation process is started

at powerup. Setting this bit to a 1 may restart the process. The default state is

a 0. The NWAYDONE bit (register 1, bit 5) is reset when this bit goes to a 1.

This bit is self-cleared when autonegotiation restarts.

0.8 (FULL_DUP)

R/W

Duplex Mode. This bit reflects the mode of operation (1 = full duplex; 0 =

half duplex). This bit is ignored when the autonegotiation enable bit (register

0, bit 12) is enabled. The default state is a 0. This bit is Ored with the F_DUP

pin.

0.7 (COLTST)

R/W

Collision Test. When this bit is set to a 1, the PHY will assert the MCOL

signal in response to MTX_EN.

0.6:0 (RESERVED)

Reserved. All bits will read 0.

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