PM7323 datasheet(89/219 Pages) PMC

89 / 219 page

STANDARD PRODUCT

PM7323 RCMP-200

DATASHEET

PMC-960543

ISSUE 2

ROUTING CONTROL, MONITORING, & POLICING

200 MBPS

Proprietary and Confidential to PMC-Sierra, Inc.

and for its Customer’s Internal Use.

AISI:

The AISI bit indicates an AIS alarm has changed state. When logic 1, the AISI

bit indicates one or more virtual connections have either entered or left the

AIS state. This bit is cleared when this register is read.

If the AISVC bit of the Master Configuration register is a logic 1, the Latest

Alarmed Virtual Connection register is updated with the VC Table index for the

virtual connection simultaneously with the setting of the AISI bit.

RDII:

The RDII bit indicates a RDI alarm has changed state. When logic 1, the RDII

bit indicates one or more virtual connections have either entered or left the

RDI state. This bit is cleared when this register is read.

If the RDIVC bit of the Master Configuration register is a logic 1, the Latest

Alarmed Virtual Connection register is updated with the VC Table index for the

virtual connection simultaneously with the setting of the RDII bit.

XPOLI:

The excessive policing indication (XPOLI) bit becomes a logic 1 upon the

receipt of a cell belonging to a connection which has a one in the most

significant bit position of one of the Non-Compliant Cell Count fields. This bit

is reset immediately after a read to this register.

If the XPOLVC bit of the Master Configuration register is a logic 1, the Latest

Alarmed Virtual Connection register is updated with the VC Table index for the

virtual connection simultaneously with the setting of the XPOLI bit.

PCELLI:

The PCELLI bit indicates a physical layer cell has been received. When logic

1, the PCELLI bit indicates one or more cells with an all zero VCI value and a

CLP=1 have been received. This bit is cleared when this register is read.

VCVALID:

The VCVALID bit becomes a logic 1 when the Latest Alarmed Virtual

Connections register (0x07) contains valid information. This bit is NOT

cleared when this register is read. This bit is cleared when the entire contents

of the Latest Alarmed Virtual Connections register (0x07) FIFO have been

read.

PM7323 Datasheet(PDF) 89 Page - PMC-Sierra, Inc