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PM7367 Datasheet(PDF) 122 Page - PMC-Sierra, Inc |
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PM7367 Datasheet(HTML) 122 Page - PMC-Sierra, Inc |
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122 / 323 page  PM7367 FREEDM-32P32 DATA SHEET PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 108 masters. In the event of a system or parity error it is recommended that the core device be reset unless the cause of the fault can be determined. PONS_E: The Report PERR on SERR enable (PONS_E) bit controls the source of system errors. When set high all parity errors will be signaled to the host via the SERRB output signal. RPWTH[4:0]: The Receive Packet Write Threshold bits (RPWTH[4:0]) controls the amount of data in the write FIFO before the GPIC begins arbitrating for the bus. The GPIC will begin requesting access to the PCI bus when the number of dwords of packet data loaded by the RMAC reaches the threshold specified by RPWTH[4:0]. |
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