PM7367 datasheet(156/323 Pages) PMC

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PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

142

ENABLE:

The ENABLE bit determines whether or not the RMAC accepts data from the

RHDL block and sends it to host memory. When set to 1, these tasks are

enabled. When set to 0, they are disabled.

LCACHE:

The large buffer cache enable bit (LCACHE) enables caching of Large Buffer

RPDRs. When LCACHE is set high, RPDRs are fetched from the RPDR

Large Buffer Free Queue in groups of up to six. When LCACHE is set low,

RPDRs are fetched one at a time.

SCACHE:

The small buffer cache enable bit (SCACHE) enables caching of Small Buffer

RPDRs. When SCACHE is set high, RPDRs are fetched from the RPDR

Small Buffer Free Queue in groups of up to six. When SCACHE is set low,

RPDRs are fetched one at a time.

RAWMAX[1:0]:

The RAWMAX[1:0] field determines how ‘raw’ (i.e. non packet delimited) data

is written to host memory. Raw data is written to buffers in host memory in

the same manner as packet delimited data. Whenever RAWMAX[1:0] + 1

buffers have been filled, the resulting buffer chain is placed in the ready

queue.

RPQ_RDYN[2:0]:

The RPQ_RDYN[2:0] field sets the number of receive packet descriptor

references (RPDRs) that must be placed onto the RPDR ready queue before

the RPDR ready interrupt (RPQRDYI) is asserted, as follows:

Table 17 – RPQ_RDYN[2:0] settings

RPQ_RDYN[2:0]

No of RPDRs

000

001

010

011

100

101

110

Reserved

PM7367 Datasheet(PDF) 156 Page - PMC-Sierra, Inc

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