Data Sheet

LT3074

analog.com

Rev 0.

41 of 62

For example, for a switching converter with less than 100kHz bandwidth and a phase margin of 50°, using the VIOC

buffer, the phase margin degrades by at most 2°. Hence, the phase margin for the switching converter (using the VIOC

pin) is at least 48°. Given that the VIOC buffer is inside the switching converter’s feedback loop, the total capacitance

on the VIOC pin must be below 20pF.

Figure 89. Programming Input-to-Output Voltage Differential

Figure 89 shows that the input-to-output differential voltage is easily programmable to support different application

needs (PSRR vs. power dissipation) using the following equation:

������������������������������������ − ������������������������������������������ + 800������������ = ������������������������������ = ������������������������������������������������������������������ ×

������1 + ������2

������1

Furthermore, if the LT3074 EN/UV pin is pulled low, the LT3074 input voltage can rise to the switching converter’s

input voltage and thus potentially violate the LT3074’s absolute maximum rating. To prevent this, the maximum

LT3074 input voltage can be set using a resistor (R3) between the VIOC and IN pins of the regulator such that:

������������������������������������(������������������) = ������������������������������������������������������������������ ×

������1 + ������2 + ������3

������1

The VIOC pin is capable of sourcing 200µA and sinking 20µA. Choose R1 and R3 values such that the VIOC pin sources

at least 10µA to ensure system stability.

Figure 93 shows a typical VIOC application used to post-regulate the output of the LT8610A buck converter. The VIOC

voltage is set at 1.1V (VINLDO – VOUTLDO is set to 300mV). The maximum LDO input voltage VINLDO(MAX) is set to 5.08V.

Thermal Considerations

For higher ambient temperatures, care should be taken in the layout of the PCB to ensure good hear sinking of the

LT3074. The IN and OUT pins at the bottom of the package should be soldered to IN and OUT planes accordingly. In

addition, the IN and OUT must be connected to large copper layers below with thermal vias; these layers spread heat

dissipated by the LT3074. Placing additional vias can reduce thermal resistance further. The die temperature is

calculated by multiplying the LT3074 power dissipation with the thermal resistance from the junction to ambient.

The internal overtemperature protection monitors the junction temperature of the LT3074. If the junction

temperature reaches approximately 168°C, the LT3074 output is shut down until the temperature drops about 7°C.

CSETCAP

4.7µF

COUT

10µF

CIN

RPG1

30kΩ

RPG2

15kΩ

RSETRES

5kΩ

800mV

51kΩ

RASELTOP

RASELBOT

0.47µF

2.2µF

LSW

R1

R3

R2

LT3074

BIAS

BIASDF

IN

OUT

SENSE

SETCAP

IMON

SDA

SCL

ALERT

ASEL

AGND

EN

VINLDO

VOUTLDO = 0.5V

IOUT(MAX) = 3A

VIOC

PG

CLKDIS

SETRES

BIASAF

DGND

PGFB

1×

+

–

VBIAS

SW

FB

VIN

EN/UV

VIN

UPSTREAM

DC-DC

CONVERTER

VFBSWITCHER