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LM7480 Datasheet(PDF) 32 Page - Texas Instruments

Part # LM7480
Description  LM7480 3-V to 65-V, Ideal Diode Controller Driving Back to Back NFETs
PDF  43 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LM7480 Datasheet(HTML) 32 Page - Texas Instruments

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During ISO 7637-2 pulse 1, the input voltage goes up to –600 V with a generator impedance of 50 Ω. This
translates to 12-A flowing through the TVS-. The clamping voltage of the TVS- cannot be same as that of 12-V
battery protection circuit. Because during the ISO 7637-2 pulse, the Anode to Cathode voltage seen is equal to (-
TVS Clamping voltage + Output capacitor voltage). For 24-V battery application, the maximum battery voltage is
32 V, then the clamping voltage of the TVS- should not exceed, 85 V – 32 V = 53 V.
Single bi-directional TVS cannot be used for 24-V battery protection because breakdown voltage for TVS+ ≥
65V, maximum clamping voltage is ≤ 53 V and the clamping voltage cannot be less than the breakdown voltage.
Two un-directional TVS connected back-back needs to be used at the input. For positive side TVS+, SMBJ58A
with the breakdown voltage of 64.4 V (minimum), 67.8 (typical) is recommended. For the negative side TVS-,
SMBJ28A with breakdown voltage close to 32 V (to withstand maximum reverse battery voltage –32 V) and
maximum clamping voltage of 42.1 V is recommended.
For 24-V battery protection, a 75-V rated MOSFET is recommended to be used along with SMBJ28A and
SMBJ58A connected back-back at the input.
10.6 Layout
10.6.1 Layout Guidelines
• For the ideal diode stage, connect A, GATE and C pins of LM74720-Q1 close to the MOSFET's SOURCE,
GATE and DRAIN pins.
• The high current path of for this solution is through the MOSFET; therefore, it is important to use thick and
short traces for source and drain of the MOSFET to minimize resistive losses.
• The GATE pin of the LM74720-Q1 must be connected to the MOSFET GATE with short trace.
• Boost converter switching currents flow into LX, CAP, GND pins and C3 (across DRAIN of the FET to GND).
The loops formed by capacitor across CAP pin and DRAIN of the FET and C3 to GND must be minimized by
placing these capacitors as close as possible. Keep the GND side of the C3 capacitor close to GND pin of
LM74720-Q1.
• Place transient suppression components like input TVS and output Schottky close to LM74720-Q1.
10.6.2 Layout Example
D
D
D
D
VIN PLANE
GND PLANE
CAP
VS
OUT
HGATE
GND
A
VSNS
SW
OV
EN/
UVLO
DGATE
C
S
S
G
S
VOUT PLANE
Q1
Q2
COUT
CVS
CCAP
D1
Figure 10-30. PCB Layout Example for Common Drain Configuration
LM7480
SNOSDD8 – DECEMBER 2022
www.ti.com
32
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