405EX datasheet(15/67 Pages) AMCC

15 / 67 page

PPC405EX – PowerPC 405EX Embedded Processor

Revision 1.09 - August 21, 2007

AMCC Proprietary

Preliminary Data Sheet

• Programmable internal/external loopback capabilities

• OPB slave (MAC) and PLB master (MAL) interfaces are 32 bits wide

• Extensive error/status vector generation for each processed packet

• VLAN tag ID supported (according to IEEE Draft 802.3ac/D1.0 standard)

• Programmable automatic source address inclusion/replacement for transmit packets

• Programmable automatic Pad/FCS stripping for receive packets

• Programmable VLAN Tag inclusion/replacement for transmit packets

• Half- or full-duplex GMII/RGMII

• Jumbo frames support

• Memory Access Layer (MAL) provides DMA capability to Ethernet channel

• Interrupt coalescence support for two transmit and two receive channels

General Purpose Timer (GPT)

The GPT provides a time base counter and system timers in addition to those defined in the processor.

Features include:

• 32-bit time base counter driven by the OPB clock

• Seven 32-bit compare timers

JTAG

Features include:

• IEEE 1149.1 test access port

• JTAG Boundary Scan Description Language (BSDL)

Refer to http://www.amcc.com/Embedded/Partners for a list of AMCC partners supplying probes for use with the

JTAG interface.

405EX Datasheet(PDF) 15 Page - Applied Micro Circuits Corporation