405EX datasheet(60/67 Pages) AMCC

60 / 67 page

PPC405EX – PowerPC 405EX Embedded Processor

AMCC Proprietary

Revision 1.09 - August 21, 2007

Preliminary Data Sheet

The following diagram illustrates the relationship among the signals involved with a DDR write operation.

Figure 7. DDR SDRAM Write Cycle Timing

Note: The timing data in the following tables is based on simulation runs using Einstimer.

Table 21. I/O Timing—DDR SDRAM TDS

Notes:

1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle.

2. Clock speed is 200MHz.

Signal Name

TDS (ns)

Minimum

Maximum

DQS0

DQS1

DQS2

DQS3

DQS4

DQS

MemData

PLB Clk

MemClkOut

Addr/Cmd

TSK

TSA

THA

TDS

TSD

THD

TSD

THD

TSA = Setup time for address and command signals to MemClkOut

TSK = Delay from rising edge of MemClkOut to rising/falling edge of signal (skew)

THA = Hold time for address and command signals from MemClkOut

TDS = Delay from rising/falling edge of clock to the rising/falling edge of DQS

TSD = Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)

THD = Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)

405EX Datasheet(PDF) 60 Page - Applied Micro Circuits Corporation