405EX datasheet(62/67 Pages) AMCC

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PPC405EX – PowerPC 405EX Embedded Processor

AMCC Proprietary

Revision 1.09 - August 21, 2007

Preliminary Data Sheet

Figure 8. DDR SDRAM Read Data Path

DDR SDRAM Read Cycle Timing

The following diagram illustrates the relationship of the signals involved with a DDR read operation.

Figure 9. DDR SDRAM Memory Data and DQS

PLB bus

Programmed

Delay

Package

Mux

Read DQS

FF: Flip-Flop

DQS

DDR 1X Clock

Mux

Data

(x32)

Read FIFO

PLB 1X Clock

Stage 2

Stage 1

Stage 3

PLB bus

[0:63]

[64:127]

DQS Rising

DQS Falling

(x32)

Coarse Delay

Cycles

Driver

Rec

MemDCFdbkD

MemDCFdbkR

Ext FeedBack

Read Start

Feedback

Data Capture

Window

DDR 1X Clock

Stage 2 Store

Oversampling

DQS aligned

CAS Lat Delay

FeedBack

Signal Gen

Fine Delay

T1 T2 T3 T4

Fine Delay

Edge Sync

Upper

Lower

Signals

pins

Q2_Ovs

FBK signal

Delay

Compare

DDR 1X Clock

Oversampling

Clock

Read Latency adjust circuit

adjust

DQS

MemData

TSD

THD

405EX Datasheet(PDF) 62 Page - Applied Micro Circuits Corporation

405EX Datasheet(HTML) 62 Page - Applied Micro Circuits Corporation

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