405EX datasheet(58/67 Pages) AMCC

58 / 67 page

PPC405EX – PowerPC 405EX Embedded Processor

AMCC Proprietary

Revision 1.09 - August 21, 2007

Preliminary Data Sheet

DDR 1/2 SDRAM I/O Specifications

The DDR SDRAM controller times its operation using the internal PLB clock signal and generates MemClkOut from

the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut is the

same frequency as the PLB clock signal and is in phase with the PLB clock signal.

Note: MemClkOut can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR

programming register. In a typical system, users advance MemClkOut by 90

°. This depends on the specific

application and requires a thorough understanding of the memory system in general (refer to the DDR

SDRAM Controller chapter in the PPC405EX Embedded Processor User’s Manual).

The signals are terminated as indicated in Figure 6 for the DDR timing data in the following sections.

Board Layout Restrictions

TBP

Clocking

TBP

Figure 6. DDR SDRAM Simulation Signal Termination Model

DDR2 SDRAM On-Die Termination Impedance Setting

For all DDR2 applications, the On-Die Termination (ODT) impedance value must be set to 75 ohms in the DIMM

Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations.

10pF

MemClkOut

120

30pF

Addr/Ctrl/Data/DQS/DM (DDR1)

VTT = SOVDD/2

PPC405EX

Addr/Ctrl (DDR2)

Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.

It is not a recommended physical circuit design for this interface. An actual interface design will depend on many

factors, including the type of memory used and the board layout.

405EX Datasheet(PDF) 58 Page - Applied Micro Circuits Corporation